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Wed, 19 Jan 2022 13:31:59 +0000 Date: Wed, 19 Jan 2022 13:31:58 +0000 Message-ID: <87czkn97ht.wl-maz@kernel.org> From: Marc Zyngier To: Qianggui Song Cc: Thomas Gleixner , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line In-Reply-To: <20220119070809.15563-3-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> <20220119070809.15563-3-qianggui.song@amlogic.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: qianggui.song@amlogic.com, tglx@linutronix.de, khilman@baylibre.com, narmstrong@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_053205_587884_5C02E4CD X-CRM114-Status: GOOD ( 23.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 19 Jan 2022 07:08:07 +0000, Qianggui Song wrote: > > Current meson gpio irqchip driver only support 8 channels for gpio irq > line, later chips may have more then 8 channels, so need to modify code > to support more. > > Signed-off-by: Qianggui Song > --- > drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c > index d90ff0b92480..eefe15e1b3a6 100644 > --- a/drivers/irqchip/irq-meson-gpio.c > +++ b/drivers/irqchip/irq-meson-gpio.c > @@ -16,7 +16,6 @@ > #include > #include > > -#define NUM_CHANNEL 8 > #define MAX_INPUT_MUX 256 > > #define REG_EDGE_POL 0x00 > @@ -60,6 +59,7 @@ struct irq_ctl_ops { > > struct meson_gpio_irq_params { > unsigned int nr_hwirq; > + unsigned int nr_channels; > bool support_edge_both; > unsigned int edge_both_offset; > unsigned int edge_single_offset; > @@ -81,6 +81,7 @@ struct meson_gpio_irq_params { > .edge_single_offset = 0, \ > .pol_low_offset = 16, \ > .pin_sel_mask = 0xff, \ > + .nr_channels = 8, \ > > #define INIT_MESON_A1_COMMON_DATA(irqs) \ > INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ > @@ -90,6 +91,7 @@ struct meson_gpio_irq_params { > .edge_single_offset = 8, \ > .pol_low_offset = 0, \ > .pin_sel_mask = 0x7f, \ > + .nr_channels = 8, \ > > static const struct meson_gpio_irq_params meson8_params = { > INIT_MESON8_COMMON_DATA(134) > @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = { > struct meson_gpio_irq_controller { > const struct meson_gpio_irq_params *params; > void __iomem *base; > - u32 channel_irqs[NUM_CHANNEL]; > - DECLARE_BITMAP(channel_map, NUM_CHANNEL); > + u32 *channel_irqs; > + unsigned long *channel_map; This really is over-engineering at its best. With your new fancy HW, you have at most 12 bits being used in this bitmap. So why not have a single unsigned long, no dynamic allocation, and simply an assertion somewhere that checks that nr_channel is never bigger than BITS_PER_LONG? Less code, less memory wasted, less problems. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel