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Sat, 12 Jun 2021 12:04:22 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ls2N9-008Qd8-Ag for linux-arm-kernel@lists.infradead.org; Sat, 12 Jun 2021 12:04:21 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E25696138C; Sat, 12 Jun 2021 12:04:18 +0000 (UTC) Received: from [185.219.108.64] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ls2N6-0079Yh-OK; Sat, 12 Jun 2021 13:04:16 +0100 Date: Sat, 12 Jun 2021 13:04:16 +0100 Message-ID: <87czsrthkv.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Catalin Marinas , Mark Rutland , Valentin Schneider , Alexandru Elisei , Russell King , kernel-team@android.com Subject: Re: [PATCH 1/3] arm64: Add cpuidle context save/restore helpers In-Reply-To: <20210611164657.GA9252@lpieralisi> References: <20210608172715.2396787-1-maz@kernel.org> <20210608172715.2396787-2-maz@kernel.org> <20210611164657.GA9252@lpieralisi> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lorenzo.pieralisi@arm.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, valentin.schneider@arm.com, alexandru.elisei@arm.com, linux@armlinux.org.uk, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210612_050419_425497_616F55C7 X-CRM114-Status: GOOD ( 29.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 11 Jun 2021 17:46:57 +0100, Lorenzo Pieralisi wrote: > > On Tue, Jun 08, 2021 at 06:27:13PM +0100, Marc Zyngier wrote: > > As we need to start doing some additional work on all idle > > paths, let's introduce a set of macros that will perform > > the work related to the GICv3 pseudo-NMI idle entry exit. > > > > Stubs are introduced to 32bit ARM for compatibility. > > As these helpers are currently unused, the is no functional > > s/the/there > > > change. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm/include/asm/cpuidle.h | 5 +++++ > > arch/arm64/include/asm/cpuidle.h | 35 ++++++++++++++++++++++++++++++++ > > 2 files changed, 40 insertions(+) > > > > diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h > > index 0d67ed682e07..1e0b8da12d96 100644 > > --- a/arch/arm/include/asm/cpuidle.h > > +++ b/arch/arm/include/asm/cpuidle.h > > @@ -49,4 +49,9 @@ extern int arm_cpuidle_suspend(int index); > > > > extern int arm_cpuidle_init(int cpu); > > > > +struct arm_cpuidle_context { }; > > + > > +#define arm_cpuidle_save_context(c) (void)c > > +#define arm_cpuidle_restore_context(c) (void)c > > + > > #endif > > diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h > > index 3c5ddb429ea2..53adad0a5c7e 100644 > > --- a/arch/arm64/include/asm/cpuidle.h > > +++ b/arch/arm64/include/asm/cpuidle.h > > @@ -18,4 +18,39 @@ static inline int arm_cpuidle_suspend(int index) > > return -EOPNOTSUPP; > > } > > #endif > > + > > +#ifdef CONFIG_ARM64_PSEUDO_NMI > > +#include > > + > > +struct arm_cpuidle_context { > > + unsigned long pmr; > > + unsigned long daif_bits; > > +}; > > + > > +#define arm_cpuidle_save_context(__c) \ > > + do { \ > > + struct arm_cpuidle_context *c = __c; \ > > + if (system_uses_irq_prio_masking()) { \ > > + c->daif_bits = read_sysreg(daif); \ > > + write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \ > > + daif); \ > > + c->pmr = gic_read_pmr(); \ > > + gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); \ > > + } \ > > + } while (0) > > + > > +#define arm_cpuidle_restore_context(__c) \ > > + do { \ > > + struct arm_cpuidle_context *c = __c; \ > > + if (system_uses_irq_prio_masking()) { \ > > + gic_write_pmr(c->pmr); \ > > + write_sysreg(c->daif_bits, daif); \ > > + } \ > > + } while (0) > > +#else > > +struct arm_cpuidle_context { }; > > + > > +#define arm_cpuidle_save_context(c) (void)c > > +#define arm_cpuidle_restore_context(c) (void)c > > +#endif > > #endif > > It looks good to me - maybe I would define it irq_context for clarity > but that's just a naming convention. would: struct arm_cpuidle_irq_context { ... }; #define arm_cpuidle_save_irq_context(c) ... #define arm_cpuidle_restore_irq_context(c) ... be OK for you? > Reviewed-by: Lorenzo Pieralisi Thanks! M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel