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Tue, 30 Mar 2021 14:24:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRFI0-003zNo-Jx for linux-arm-kernel@lists.infradead.org; Tue, 30 Mar 2021 14:24:18 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 23C14619BD; Tue, 30 Mar 2021 14:24:15 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lRFHx-004hMq-0o; Tue, 30 Mar 2021 15:24:13 +0100 Date: Tue, 30 Mar 2021 15:24:12 +0100 Message-ID: <87czvgra7n.wl-maz@kernel.org> From: Marc Zyngier To: Ard Biesheuvel Cc: Linux ARM , Will Deacon , Android Kernel Team , Anshuman Khandual , Steve Capper , Catalin Marinas , kvmarm , Quentin Perret Subject: Re: [PATCH] arm64: kvm: handle 52-bit VA regions correctly under nVHE In-Reply-To: References: <20210330112126.463336-1-ardb@kernel.org> <87lfa4rety.wl-maz@kernel.org> <87k0pordvw.wl-maz@kernel.org> <87h7ksrbih.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: ardb@kernel.org, linux-arm-kernel@lists.infradead.org, will@kernel.org, kernel-team@android.com, anshuman.khandual@arm.com, steve.capper@arm.com, catalin.marinas@arm.com, kvmarm@lists.cs.columbia.edu, qperret@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_152417_333036_005DED28 X-CRM114-Status: GOOD ( 23.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 30 Mar 2021 14:58:39 +0100, Ard Biesheuvel wrote: > > On Tue, 30 Mar 2021 at 15:56, Marc Zyngier wrote: > > > > On Tue, 30 Mar 2021 14:15:19 +0100, > > Ard Biesheuvel wrote: [...] > > > It seems to me that the only way to solve this is to permit the idmap > > > and the hyp linear region to overlap, and use the 2^47 byte window at > > > the top of the address space for the hyp private mappings instead of > > > the one at the bottom. > > > > But that's the hard problem I want to avoid thinking of. > > > > We need to ensure that there is no EL1 VA that is congruent with the > > idmap over the kern_hyp_va() transformation. It means imposing > > restrictions over the EL1 linear map, and prevent any allocation that > > would result in this overlap (and that is including text). > > > > How do we do that? > > > > A phys to virt offset of 0x0 is perfectly acceptable, no? The only > difference is that the idmapped bits are in another part of the VA > space. What do we lose by doing that? If that's acceptable for LVA, why don't we do it across the board? It feels like KASLR and EL2 randomisation are in the way... M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel