From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52405CA5FCE for ; Mon, 5 Oct 2026 08:27:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fsKzr1wwNvOjG1lYsOOgfAPocI7bU4FNx1neeTdXdCU=; b=ctDLTeAGURYMtX2llp6jC5YcJB Fi2lP/GY29EoV+M8qrvFzT/KvzN8dUkF4khdblkoIikrrKLZBmmlFx9aaUKalxiYWU0PnynfhJ+rw jZ/33+EewWoc51vo36u9PP6KgK6CU53nxaByiwDw8Y2X39gcWZzNKDGxbQ7+n4rfM49N9Nj+RLZA3 kt+GLH8Fnz2mgXmQdZhjNdYBWM4Q2XP4md2mzPOlvn4sK+RKQ3pb16iOYIOLfu7gd/X0hCYKX1cey hNM/ZTiRxqKxfSMYMVjz6IBpXvEhTChkeTnX5WOEwHuWWEj9rhQ30QwK2CQ0QEp88x6RQt5CD+gHA 1R5Qa+5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xDe2q-0000000FsjP-07E0; Mon, 05 Oct 2026 08:27:36 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1xDe2p-0000000FsjC-0aPe for linux-arm-kernel@lists.infradead.org; Mon, 05 Oct 2026 08:27:35 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 8AA1F6022B; Mon, 5 Oct 2026 08:27:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 40A7A1F000FF; Mon, 5 Oct 2026 08:27:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791188854; bh=fsKzr1wwNvOjG1lYsOOgfAPocI7bU4FNx1neeTdXdCU=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=ZFgOJSusJIoSOi11shbnQnrlSzUGgYbaD3c8YdF90OeX7PaXk7RuxWk0/vu9lA0Vj nUqK2foIIZ5QFyit1d67UQBHX7OkLSBMI8/G+6tmHeTUVMzp2th5bIY7SseS8ZL0sT bgmcxpLAHJOk7axStkf3y9j1GEnI0teRW0fcb1KwO5YX6na+1uLW1bdzCM0vVYT58i x3wWG+N/q5f9hzKRfeC3fyYhfWDCb8iE7gSxhkZ6QkAl0OmbMlQykWSGf8aZwyMGVH 0o9PO+y9+MkeUQjKL06AY/4euFiG5MNwK/hm9+JQXTpc/dq2fmvOTxIbF/afYdgjwO DyWJEkRhLxFHQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xDe2l-0000000GzC6-42XU; Mon, 05 Oct 2026 08:27:32 +0000 Date: Mon, 05 Oct 2026 09:30:39 +0100 Message-ID: <87ece435xs.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, vdonnefort@google.com, qperret@google.com, tabba@google.com, mark.rutland@arm.com Subject: Re: [PATCH] KVM: arm64: Pend host SErrors for protected vCPUs through HCR_EL2.VSE In-Reply-To: <20261005050352.836980-1-fuad.tabba@linux.dev> References: <20261005050352.836980-1-fuad.tabba@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: fuad.tabba@linux.dev, oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, vdonnefort@google.com, qperret@google.com, tabba@google.com, mark.rutland@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 05 Oct 2026 06:03:52 +0100, Fuad Tabba wrote: > > kvm_inject_serror_esr() reads PSTATE.A and SCTLR2_EL1.NMEA to decide > whether to emulate the SError's exception entry or pend it through > HCR_EL2.VSE. For a protected vCPU, the host's copy of those is stale, > and when it reads as unmasked KVM emulates the entry on that copy. EL2 > never delivers it as an SError: its entry handler turns the pending > exception into an external abort on the trapped access, and an MMIO > completion still pending trips WARN_ON(INCREMENT_PC). > > Always pend through HCR_EL2.VSE for a protected vCPU. EL2 forwards it, > and the guest's own masking decides when the SError is taken. > > Fixes: 872383bd12e11 ("KVM: arm64: Add per-EC entry/exit state marshalling for protected guests") > Reported-by: Sashiko > Closes: https://lore.kernel.org/all/20261001142109.794CA1F000FF@smtp.kernel.org/ > Signed-off-by: Fuad Tabba > --- > Applies on kvmarm/next. A follow-up to "KVM: arm64: Confine protected VM > vCPU state to EL2" [1], from Sashiko's review of its v4 patch 12. > > [1] https://lore.kernel.org/all/20261001135711.1640520-1-fuad.tabba@linux.dev/ > > arch/arm64/kvm/inject_fault.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c > index d6c4fc16f8795..49a342b078365 100644 > --- a/arch/arm64/kvm/inject_fault.c > +++ b/arch/arm64/kvm/inject_fault.c > @@ -378,8 +378,11 @@ int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr) > * > * As we're emulating the SError injection we need to explicitly populate > * ESR_ELx.EC because hardware will not do it on our behalf. > + * > + * A protected vCPU's PSTATE and SCTLR2_EL1 live at EL2, so pend through > + * HCR_EL2.VSE and let the guest's own masking apply. > */ > - if (!serror_is_masked(vcpu)) { > + if (!vcpu_is_protected(vcpu) && !serror_is_masked(vcpu)) { > pend_serror_exception(vcpu); > esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SERROR) | ESR_ELx_IL; > vcpu_write_sys_reg(vcpu, esr, exception_esr_elx(vcpu)); > I thought we had discussed that one before (or am I making things up?). Why can't the host always evaluate serror_is_masked() as true? Given that PSTATE is never synced back to the host, it would only be a matter of set PSTATE.A==1 at vcpu creation time. It'd be more palatable than this sprinkling of vcpu_is_protected(), which really do not scale. Thanks, M. -- Jazz isn't dead. It just smells funny.