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Thu, 01 Jun 2023 12:59:29 +0100 Date: Thu, 01 Jun 2023 12:59:24 +0100 Message-ID: <87edmvpf4z.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Zenghui Yu , Quentin Perret , Will Deacon , Fuad Tabba Subject: Re: [PATCH v2 06/17] arm64: Allow EL1 physical timer access when running VHE In-Reply-To: References: <20230526143348.4072074-1-maz@kernel.org> <20230526143348.4072074-7-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 109.23.4.90 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, qperret@google.com, will@kernel.org, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230601_045933_245534_C0394E69 X-CRM114-Status: GOOD ( 27.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 01 Jun 2023 07:34:19 +0100, Oliver Upton wrote: > > Hey Marc, > > On Fri, May 26, 2023 at 03:33:37PM +0100, Marc Zyngier wrote: > > To initialise the timer access from EL2 when HCR_EL2.E2H is set, > > we must make use the CNTHCTL_EL2 formap used is appropriate. > > > > This amounts to shifting the timer/counter enable bits by 10 > > to the left. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/el2_setup.h | 5 +++++ > > arch/arm64/kvm/hyp/nvhe/hyp-init.S | 9 +++++++++ > > 2 files changed, 14 insertions(+) > > > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > > index 037724b19c5c..225bf1f2514d 100644 > > --- a/arch/arm64/include/asm/el2_setup.h > > +++ b/arch/arm64/include/asm/el2_setup.h > > @@ -34,6 +34,11 @@ > > */ > > .macro __init_el2_timers > > mov x0, #3 // Enable EL1 physical timers > > + mrs x1, hcr_el2 > > + and x1, x1, #HCR_E2H > > + cbz x1, .LnVHE_\@ > > + lsl x0, x0, #10 > > +.LnVHE_\@: > > msr cnthctl_el2, x0 > > msr cntvoff_el2, xzr // Clear virtual offset > > .endm > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > index a6d67c2bb5ae..f9ee10e29497 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > @@ -95,6 +95,15 @@ SYM_CODE_START_LOCAL(___kvm_hyp_init) > > ldr x1, [x0, #NVHE_INIT_HCR_EL2] > > msr hcr_el2, x1 > > > > + mov x2, #HCR_E2H > > + and x2, x1, x2 > > + cbz x2, 1f > > + > > + mrs x1, cnthctl_el2 > > + and x1, x1, #~(BIT(0) | BIT(1)) > > + orr x1, x1, #(BIT(10) | BIT(11)) > > + msr cnthctl_el2, x1 > > +1: > > Can this be done with an alternative block keyed on ARM64_KVM_HVHE? > I get that __init_el2_timers needs to run before the cpu caps have been > evaluated, but I don't think the same applies for ___kvm_hyp_init I don't mind either way. My reasoning was that this code is hardly ever executed, so the performance benefit of alternatives don't really apply here (and the resulting object is smaller by 28 bytes... ;-). Happy to change it if you think this makes sense. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel