* [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay
@ 2020-02-25 11:45 Russell King
2020-02-25 15:43 ` Baruch Siach
2020-03-13 20:13 ` Gregory CLEMENT
0 siblings, 2 replies; 3+ messages in thread
From: Russell King @ 2020-02-25 11:45 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Mark Rutland, Andrew Lunn, Baruch Siach, Jason Cooper, devicetree,
Rob Herring, linux-arm-kernel, Sebastian Hesselbarth
If the mv88e6xxx DSA driver is built as a module, it causes the
ethernet driver to re-probe when it's loaded. This in turn causes
the gigabit PHY to be momentarily reset and reprogrammed. However,
we attempt to reprogram the PHY immediately after deasserting reset,
and the PHY ignores the writes.
This results in the PHY operating in the wrong mode, and the copper
link states down.
Set a reset deassert delay of 10ms for the gigabit PHY to avoid this.
Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index bd881497b872..dc531d136273 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -367,6 +367,7 @@
pinctrl-0 = <&cp0_copper_eth_phy_reset>;
reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
};
switch0: switch0@4 {
--
2.20.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay
2020-02-25 11:45 [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay Russell King
@ 2020-02-25 15:43 ` Baruch Siach
2020-03-13 20:13 ` Gregory CLEMENT
1 sibling, 0 replies; 3+ messages in thread
From: Baruch Siach @ 2020-02-25 15:43 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland, Andrew Lunn, Jason Cooper, devicetree,
Gregory CLEMENT, Rob Herring, linux-arm-kernel,
Sebastian Hesselbarth
Hi Russell,
On Tue, Feb 25, 2020 at 11:45:12AM +0000, Russell King wrote:
> If the mv88e6xxx DSA driver is built as a module, it causes the
> ethernet driver to re-probe when it's loaded. This in turn causes
> the gigabit PHY to be momentarily reset and reprogrammed. However,
> we attempt to reprogram the PHY immediately after deasserting reset,
> and the PHY ignores the writes.
>
> This results in the PHY operating in the wrong mode, and the copper
> link states down.
>
> Set a reset deassert delay of 10ms for the gigabit PHY to avoid this.
>
> Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Thanks,
baruch
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index bd881497b872..dc531d136273 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -367,6 +367,7 @@
> pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> + reset-deassert-us = <10000>;
> };
>
> switch0: switch0@4 {
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay
2020-02-25 11:45 [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay Russell King
2020-02-25 15:43 ` Baruch Siach
@ 2020-03-13 20:13 ` Gregory CLEMENT
1 sibling, 0 replies; 3+ messages in thread
From: Gregory CLEMENT @ 2020-03-13 20:13 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland, Andrew Lunn, Baruch Siach, Jason Cooper, devicetree,
Rob Herring, linux-arm-kernel, Sebastian Hesselbarth
Hi Russell,
> If the mv88e6xxx DSA driver is built as a module, it causes the
> ethernet driver to re-probe when it's loaded. This in turn causes
> the gigabit PHY to be momentarily reset and reprogrammed. However,
> we attempt to reprogram the PHY immediately after deasserting reset,
> and the PHY ignores the writes.
>
> This results in the PHY operating in the wrong mode, and the copper
> link states down.
>
> Set a reset deassert delay of 10ms for the gigabit PHY to avoid this.
>
> Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index bd881497b872..dc531d136273 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -367,6 +367,7 @@
> pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> + reset-deassert-us = <10000>;
> };
>
> switch0: switch0@4 {
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-02-25 11:45 [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay Russell King
2020-02-25 15:43 ` Baruch Siach
2020-03-13 20:13 ` Gregory CLEMENT
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