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Mon, 07 Mar 2022 11:35:14 +0000 Date: Mon, 07 Mar 2022 11:35:14 +0000 Message-ID: <87fsnu0zd9.wl-maz@kernel.org> From: Marc Zyngier To: Hector Martin Cc: Thomas Gleixner , Rob Herring , Sven Peter , Alyssa Rosenzweig , Mark Kettenis , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support In-Reply-To: References: <20220224130741.63924-1-marcan@marcan.st> <20220224130741.63924-4-marcan@marcan.st> <87mtif2eoz.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: marcan@marcan.st, tglx@linutronix.de, robh+dt@kernel.org, sven@svenpeter.dev, alyssa@rosenzweig.io, mark.kettenis@xs4all.nl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220307_033518_300191_06B2BC1E X-CRM114-Status: GOOD ( 19.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, 27 Feb 2022 15:33:54 +0000, Hector Martin wrote: > > On 25/02/2022 23.39, Marc Zyngier wrote: > > On Thu, 24 Feb 2022 13:07:37 +0000, > >> if (!(pending & irq_bit) && > >> - (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) > >> - send |= AIC_IPI_SEND_CPU(cpu); > >> + (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) { > >> + if (static_branch_likely(&use_fast_ipi)) > >> + aic_ipi_send_fast(cpu); > > > > OK, this is suffering from the same issue that GICv3 has, which is > > that memory barriers don't provide order against sysregs. You need a > > DSB for that, which is a pain. Something like this: > > Doesn't the control flow here guarantee the ordering? atomic_read() must > complete before the sysreg is written since there is a control flow > dependency, and the prior atomic/barrier dance ensures that read is > ordered properly with everything that comes before it. Yes, you're right. Mixing memory ordering and control dependency hurts my head badly, but hey, why not. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel