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Tue, 30 Mar 2021 14:00:33 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lREuq-003uKa-KC for linux-arm-kernel@lists.infradead.org; Tue, 30 Mar 2021 14:00:23 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 020996044F; Tue, 30 Mar 2021 14:00:19 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lREum-004h4b-Tm; Tue, 30 Mar 2021 15:00:17 +0100 Date: Tue, 30 Mar 2021 15:00:16 +0100 Message-ID: <87ft0crbbj.wl-maz@kernel.org> From: Marc Zyngier To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, anshuman.khandual@arm.com, catalin.marinas@arm.com, Will Deacon , Mark Rutland , Alexandru Elisei Subject: Re: [PATCH v5 07/19] arm64: kvm: Enable access to TRBE support for host In-Reply-To: References: <20210323120647.454211-1-suzuki.poulose@arm.com> <20210323120647.454211-8-suzuki.poulose@arm.com> <87r1jxq7ax.wl-maz@kernel.org> <87mtukrg6o.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, anshuman.khandual@arm.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, Alexandru.Elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_150021_575745_DC65FA43 X-CRM114-Status: GOOD ( 23.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 30 Mar 2021 14:34:23 +0100, Suzuki K Poulose wrote: > > On 30/03/2021 13:15, Marc Zyngier wrote: > > On Tue, 30 Mar 2021 12:12:49 +0100, > > Suzuki K Poulose wrote: [...] > >> May be we could do this check at kvm_arch_vcpu_load()/put() ? > > > > That would extend the tracing blackout period enormously, wouldn't it? > > I'm not sure that's the best thing to do... > > Sorry for not making this clear. We could check if the SPE/TRBE is > available on this CPU (including the PMB/TRB_IDR bits and a set a flag > in the VCPU on every kvm_arch_vcpu_load() and cleared on put. > The actual switching code could check this flag and check if the unit > is enabled and then do the actual save/restore as we do below. > (We may be able to even check if unit is enabled there, need to double > check this.) Ah, gotcha. Yes, this seems like a reasonable thing to do. We have the per-vcpu debug flags already, and you could piggy-back on that. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel