* [PATCH v2 0/4] Exynos 5410 Dual cluster support
@ 2013-10-14 15:08 Vyacheslav Tyrtov
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
` (4 more replies)
0 siblings, 5 replies; 25+ messages in thread
From: Vyacheslav Tyrtov @ 2013-10-14 15:08 UTC (permalink / raw)
To: linux-arm-kernel
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
Patches add new platform description, support of clock controller,
dual cluster support and device tree for Exynos 5410
Has been build on v3.12-rc5.
Has been tested on Exynos 5410 reference board (exynos_defconfig).
Thanks,
Vyacheslav.
Changelog:
v2:
In drivers/clk/samsung/clk-exynos5410.c
1. Clock driver converted to use preprocessor macros instead of enums.
Clock IDs now defined in include/dt-bindings/clock/exynos5410.h.
2. Unused spinlock removed.
3. Function exynos5410_clk_init defined as static.
Struct exynos5410_fixed_rate_ext_clks defined as static.
Struct exynos5410_mux_clks defined as static.
Struct exynos5410_div_clks defined as static.
Struct exynos5410_gate_clks defined as static.
4. Removed aliases.
5. Pll's magic register offsets defined as preprocessor macros.
6. Redundant check of device_node pointer removed.
In arch/arm/boot/dts/exynos5410.dtsi
1. dwmmcX nodes renamed to mmc.
dwmmc_X renamed to mmc_X.
dwmmc status="disabled" field added.
fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts
2. Blank lines added where necessary.
3. cpu@ suffixes corrected.
4. edcs node removed.
5. Hexadecimal characters case corrected.
6. Clock IDs replaced with preprocessor macros.
In arch/arm/boot/dts/exynos5410-smdk5410.dts
1. status = "okay" field added to mmc nodes.
In arch/arm/mach-exynos/edcs.c
1. "kfs_" prefix replaced with "edcs_"
2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values.
3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c
4. mcpm_sync_init() call added.
5. power management functions reworked.
Other
1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected.
2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and
ARM_CCI in arch/arm/mach-exynos/Kconfig.
3. edcs_status driver removed.
Tarek Dakhran (4):
ARM: EXYNOS: Add support for EXYNOS5410 SoC
clk: exynos5410: register clocks using common clock framework
ARM: EXYNOS: add Exynos Dual Cluster Support
ARM: dts: Add initial device tree support for EXYNOS5410
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 +++++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++++++++++++++++
arch/arm/mach-exynos/Kconfig | 12 +
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/common.c | 18 ++
arch/arm/mach-exynos/edcs.c | 270 +++++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251 +++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 175 +++++++++++++
14 files changed, 1051 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
create mode 100644 arch/arm/mach-exynos/edcs.c
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
--
1.8.1.5
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
@ 2013-10-14 15:08 ` Vyacheslav Tyrtov
2013-11-01 17:08 ` Tomasz Figa
2013-11-01 21:52 ` Rob Herring
2013-10-14 15:08 ` [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
` (3 subsequent siblings)
4 siblings, 2 replies; 25+ messages in thread
From: Vyacheslav Tyrtov @ 2013-10-14 15:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/mach-exynos/Kconfig | 12 ++++++++++++
arch/arm/mach-exynos/common.c | 18 ++++++++++++++++++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define EXYNOS5250_SOC_ID 0x43520000
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE5420000
#define EXYNOS5440_SOC_ID 0xE5440000
#define EXYNOS5_SOC_MASK 0xFFFFF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
@@ -144,6 +146,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5250() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410() is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5420)
# define soc_is_exynos5420() is_samsung_exynos5420()
#else
--
1.8.1.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
@ 2013-10-14 15:08 ` Vyacheslav Tyrtov
2013-10-22 9:44 ` Mike Turquette
2013-11-01 16:58 ` Tomasz Figa
2013-10-14 15:08 ` [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support Vyacheslav Tyrtov
` (2 subsequent siblings)
4 siblings, 2 replies; 25+ messages in thread
From: Vyacheslav Tyrtov @ 2013-10-14 15:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251 +++++++++++++++++++++
include/dt-bindings/clock/exynos5410.h | 175 ++++++++++++++
4 files changed, 464 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 0000000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller at 0x10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial at 12C20000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C00000 0x100>;
+ interrupts = <0 51 0>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 0000000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include <dt-bindings/clock/exynos5410.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU 0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC0 0x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC 0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long exynos5410_clk_regs[] __initdata = {
+ SRC_CPU,
+ DIV_CPU0,
+ SRC_CPERI1,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_PERIC0,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_FSYS,
+ SRC_PERIC0,
+ SRC_MASK_FSYS,
+ SRC_MASK_PERIC0,
+ GATE_BUS_FSYS0,
+ GATE_IP_FSYS,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+ SRC_CDREX,
+ SRC_KFC,
+ DIV_KFC0,
+};
+
+/* list of all parent clocks */
+PNAME(apll_p) = { "fin_pll", "fout_apll", };
+PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
+PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
+PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
+PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
+
+PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
+PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
+
+PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
+PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+
+PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
+ "none", "none", "sclk_mpll_bpll",
+ "none", "none", "sclk_cpll" };
+
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock exynos5410_frt_ext_clks[] __initdata = {
+ FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
+};
+
+static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
+ MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+
+ MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
+ MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+
+ MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
+ MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
+
+ MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+ MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
+
+ MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
+
+ MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
+
+ MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
+ MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
+ MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+
+ MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
+ MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
+ MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+
+ MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
+ MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
+};
+
+static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
+ DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+ DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
+
+ DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
+ DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
+ DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
+ DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
+
+ DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
+ DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
+ DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
+
+ DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
+ DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+
+ DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+ DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
+ DIV_F(0, "div_mmc_pre0", "div_mmc0",
+ DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre1", "div_mmc1",
+ DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+ DIV_F(0, "div_mmc_pre2", "div_mmc2",
+ DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+
+ DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+ DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+ DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+ DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+
+ DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+ DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
+};
+
+static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
+ GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+
+ GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
+ SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
+ SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
+ SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
+ GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
+ GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+
+ GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+ GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+ GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+
+ GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
+ SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
+ SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
+};
+
+static struct of_device_id ext_clk_match[] __initdata = {
+ { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
+ { },
+};
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+ exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
+ NULL, 0);
+ samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
+ ARRAY_SIZE(exynos5410_frt_ext_clks),
+ ext_clk_match);
+ samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
+ reg_base);
+
+ samsung_clk_register_mux(exynos5410_mux_clks,
+ ARRAY_SIZE(exynos5410_mux_clks));
+ samsung_clk_register_div(exynos5410_div_clks,
+ ARRAY_SIZE(exynos5410_div_clks));
+ samsung_clk_register_gate(exynos5410_gate_clks,
+ ARRAY_SIZE(exynos5410_gate_clks));
+
+ pr_debug("Exynos5410: clock setup completed.\n");
+}
+CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000..9b4a58b
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,175 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_DPLL 4
+#define CLK_FOUT_EPLL 5
+#define CLK_FOUT_RPLL 6
+#define CLK_FOUT_IPLL 7
+#define CLK_FOUT_SPLL 8
+#define CLK_FOUT_VPLL 9
+#define CLK_FOUT_MPLL 10
+#define CLK_FOUT_BPLL 11
+#define CLK_FOUT_KPLL 12
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+#define CLK_SCLK_SPI0 135
+#define CLK_SCLK_SPI1 136
+#define CLK_SCLK_SPI2 137
+#define CLK_SCLK_I2S1 138
+#define CLK_SCLK_I2S2 139
+#define CLK_SCLK_PCM1 140
+#define CLK_SCLK_PCM2 141
+#define CLK_SCLK_SPDIF 142
+#define CLK_SCLK_HDMI 143
+#define CLK_SCLK_PIXEL 144
+#define CLK_SCLK_DP1 145
+#define CLK_SCLK_MIPI1 146
+#define CLK_SCLK_FIMD1 147
+#define CLK_SCLK_MAUDIO0 148
+#define CLK_SCLK_MAUPCM0 149
+#define CLK_SCLK_USBD300 150
+#define CLK_SCLK_USBD301 151
+#define CLK_SCLK_USBPHY300 152
+#define CLK_SCLK_USBPHY301 153
+#define CLK_SCLK_UNIPRO 154
+#define CLK_SCLK_PWM 155
+#define CLK_SCLK_GSCL_WA 156
+#define CLK_SCLK_GSCL_WB 157
+#define CLK_SCLK_HDMIPHY 158
+
+/* gate clocks */
+#define CLK_ACLK66_PERIC 256
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_I2C0 261
+#define CLK_I2C1 262
+#define CLK_I2C2 263
+#define CLK_I2C3 264
+#define CLK_I2C4 265
+#define CLK_I2C5 266
+#define CLK_I2C6 267
+#define CLK_I2C7 268
+#define CLK_I2C_HDMI 269
+#define CLK_TSADC 270
+#define CLK_SPI0 271
+#define CLK_SPI1 272
+#define CLK_SPI2 273
+#define CLK_KEYIF 274
+#define CLK_I2S1 275
+#define CLK_I2S2 276
+#define CLK_PCM1 277
+#define CLK_PCM2 278
+#define CLK_PWM 279
+#define CLK_SPDIF 280
+#define CLK_I2C8 281
+#define CLK_I2C9 282
+#define CLK_I2C10 283
+#define CLK_ACLK66_PSGEN 300
+#define CLK_CHIPID 301
+#define CLK_SYSREG 302
+#define CLK_TZPC0 303
+#define CLK_TZPC1 304
+#define CLK_TZPC2 305
+#define CLK_TZPC3 306
+#define CLK_TZPC4 307
+#define CLK_TZPC5 308
+#define CLK_TZPC6 309
+#define CLK_TZPC7 310
+#define CLK_TZPC8 311
+#define CLK_TZPC9 312
+#define CLK_HDMI_CEC 313
+#define CLK_SECKEY 314
+#define CLK_MCT 315
+#define CLK_WDT 316
+#define CLK_RTC 317
+#define CLK_TMU 318
+#define CLK_TMU_GPU 319
+#define CLK_PCLK66_GPIO 330
+#define CLK_ACLK200_FSYS2 350
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+#define CLK_SROMC 354
+#define CLK_UFS 355
+#define CLK_ACLK200_FSYS 360
+#define CLK_TSI 361
+#define CLK_PDMA0 362
+#define CLK_PDMA1 363
+#define CLK_RTIC 364
+#define CLK_USBH20 365
+#define CLK_USBD300 366
+#define CLK_USBD301 367
+#define CLK_ACLK400_MSCL 380
+#define CLK_MSCL0 381
+#define CLK_MSCL1 382
+#define CLK_MSCL2 383
+#define CLK_SMMU_MSCL0 384
+#define CLK_SMMU_MSCL1 385
+#define CLK_SMMU_MSCL2 386
+#define CLK_ACLK333 400
+#define CLK_MFC 401
+#define CLK_SMMU_MFCL 402
+#define CLK_SMMU_MFCR 403
+#define CLK_ACLK200_DISP1 410
+#define CLK_DSIM1 411
+#define CLK_DP1 412
+#define CLK_HDMI 413
+#define CLK_ACLK300_DISP1 420
+#define CLK_FIMD1 421
+#define CLK_SMMU_FIMD1 422
+#define CLK_ACLK166 430
+#define CLK_MIXER 431
+#define CLK_ACLK266 440
+#define CLK_ROTATOR 441
+#define CLK_MDMA1 442
+#define CLK_SMMU_ROTATOR 443
+#define CLK_SMMU_MDMA1 444
+#define CLK_ACLK300_JPEG 450
+#define CLK_JPEG 451
+#define CLK_JPEG2 452
+#define CLK_SMMU_JPEG 453
+#define CLK_ACLK300_GSCL 460
+#define CLK_SMMU_GSCL0 461
+#define CLK_SMMU_GSCL1 462
+#define CLK_GSCL_WA 463
+#define CLK_GSCL_WB 464
+#define CLK_GSCL0 465
+#define CLK_GSCL1 466
+#define CLK_CLK_3AA 467
+#define CLK_ACLK266_G2D 470
+#define CLK_SSS 471
+#define CLK_SLIM_SSS 472
+#define CLK_MDMA0 473
+#define CLK_ACLK333_G2D 480
+#define CLK_G2D 481
+#define CLK_ACLK333_432_GSCL 490
+#define CLK_SMMU_3AA 491
+#define CLK_SMMU_FIMCL0 492
+#define CLK_SMMU_FIMCL1 493
+#define CLK_SMMU_FIMCL3 494
+#define CLK_FIMC_LITE3 495
+#define CLK_ACLK_G3D 500
+#define CLK_G3D 501
+#define CLK_SMMU_MIXER 502
+
+/* mux clocks */
+#define CLK_MOUT_HDMI 640
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL 768
+#define CLK_NR_CLKS 769
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
--
1.8.1.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
2013-10-14 15:08 ` [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
@ 2013-10-14 15:08 ` Vyacheslav Tyrtov
2013-10-17 10:45 ` Daniel Lezcano
2013-10-25 10:06 ` Aliaksei Katovich
2013-10-14 15:08 ` [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410 Vyacheslav Tyrtov
2013-10-16 22:15 ` [PATCH v2 0/4] Exynos 5410 Dual cluster support Kevin Hilman
4 siblings, 2 replies; 25+ messages in thread
From: Vyacheslav Tyrtov @ 2013-10-14 15:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 270 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 272 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 0000000..e304bd9
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,270 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran <t.dakhran@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <linux/arm-cci.h>
+#include <mach/regs-pmu.h>
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION \
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0 (S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr) (REG_CPU_STATE_ADDR0 + \
+ _nr * EDCS_CPUS_PER_CLUSTER)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EDCS_CORE_STATUS(offset)) & 0x3) != value)
+ __raw_writel(value, EDCS_CORE_CONFIGURATION(offset));
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ __raw_writel(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(&edcs_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, 0x2);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+ * The only possible values are:
+ * 0 = CPU down
+ * 1 = CPU (still) up
+ * 2 = CPU requested to be up before it had a chance
+ * to actually make itself down.
+ * Any other value is a bug.
+ */
+ BUG();
+ }
+
+ arch_spin_unlock(&edcs_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(&edcs_lock);
+ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+ edcs_use_count[cpu][cluster]--;
+ if (edcs_use_count[cpu][cluster] == 0) {
+ --core_count[cluster];
+ if (core_count[cluster] == 0)
+ last_man = true;
+ } else if (edcs_use_count[cpu][cluster] == 1) {
+ /*
+ * A power_up request went ahead of us.
+ * Even if we do not want to shut this CPU down,
+ * the caller expects a certain state as if the WFI
+ * was aborted. So let's continue with cache cleaning.
+ */
+ skip_wfi = true;
+ } else
+ BUG();
+
+ if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+ arch_spin_unlock(&edcs_lock);
+
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+ /*
+ * On the Cortex-A15 we need to disable
+ * L2 prefetching before flushing the cache.
+ */
+ asm volatile(
+ "mcr p15, 1, %0, c15, c0, 3\n\t"
+ "isb\n\t"
+ "dsb"
+ : : "r" (0x400));
+ }
+
+ /*
+ * We need to disable and flush the whole (L1 and L2) cache.
+ * Let's do it in the safest possible way i.e. with
+ * no memory access within the following sequence
+ * including the stack.
+ *
+ * Note: fp is preserved to the stack explicitly prior doing
+ * this since adding it to the clobber list is incompatible
+ * with having CONFIG_FRAME_POINTER=y.
+ */
+ asm volatile(
+ "str fp, [sp, #-4]!\n\t"
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
+ "bic r0, r0, #"__stringify(CR_C)"\n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
+ "isb\n\t"
+ "bl v7_flush_dcache_all\n\t"
+ "clrex\n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
+ "isb\n\t"
+ "dsb\n\t"
+ "ldr fp, [sp], #4"
+ : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r9", "r10", "lr", "memory");
+
+ cci_disable_port_by_cpu(mpidr);
+
+ __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+
+ } else {
+ arch_spin_unlock(&edcs_lock);
+ /*
+ * We need to disable and flush only the L1 cache.
+ * Let's do it in the safest possible way as above.
+ */
+ asm volatile(
+ "str fp, [sp, #-4]!\n\t"
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
+ "bic r0, r0, #"__stringify(CR_C)"\n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
+ "isb\n\t"
+ "bl v7_flush_dcache_louis\n\t"
+ "clrex\n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
+ "isb\n\t"
+ "dsb\n\t"
+ "ldr fp, [sp], #4"
+ : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r9", "r10", "lr", "memory");
+
+ }
+ __mcpm_cpu_down(cpu, cluster);
+
+ if (!skip_wfi) {
+ exynos_core_power_down(cpu, cluster);
+ wfi();
+ }
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+ .power_up = exynos_power_up,
+ .power_down = exynos_power_down,
+};
+
+static void __init edcs_data_init(void)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+ edcs_use_count[cpu][cluster] = 1;
+ ++core_count[cluster];
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked edcs_power_up_setup(unsigned int affinity_level)
+{
+ asm volatile ("\n"
+ "b cci_enable_port_for_self");
+}
+
+static int __init edcs_init(void)
+{
+ int ret;
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "samsung,exynos5410");
+ if (!node)
+ return -ENODEV;
+
+ if (!cci_probed())
+ return -ENODEV;
+
+ /*
+ * Future entries into the kernel can now go
+ * through the cluster entry vectors.
+ */
+ __raw_writel(virt_to_phys(mcpm_entry_point),
+ S5P_VA_SYSRAM_NS + 0x1c);
+
+ edcs_data_init();
+ mcpm_smp_set_ops();
+
+ ret = mcpm_platform_register(&exynos_power_ops);
+ if (!ret) {
+ mcpm_sync_init(edcs_power_up_setup);
+ pr_info("EDCS power management initialized\n");
+ }
+ return ret;
+}
+
+early_initcall(edcs_init);
--
1.8.1.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
` (2 preceding siblings ...)
2013-10-14 15:08 ` [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support Vyacheslav Tyrtov
@ 2013-10-14 15:08 ` Vyacheslav Tyrtov
2013-11-01 17:09 ` Tomasz Figa
2013-10-16 22:15 ` [PATCH v2 0/4] Exynos 5410 Dual cluster support Kevin Hilman
4 siblings, 1 reply; 25+ messages in thread
From: Vyacheslav Tyrtov @ 2013-10-14 15:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarek Dakhran <t.dakhran@samsung.com>
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++++++++++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 0000000..c3d0b32
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,clock-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ mmc at 12200000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc at 12220000 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 0000000..92a5a73
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/exynos5410.h>
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ cci-control-port = <&cci_control2>;
+ clock-frequency = <1600000000>;
+ };
+
+ CPU4: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <1200000000>;
+ };
+
+ CPU5: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <1200000000>;
+ };
+
+ CPU6: cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <1200000000>;
+ };
+
+ CPU7: cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cci-control-port = <&cci_control1>;
+ clock-frequency = <1200000000>;
+ };
+ };
+
+ cci at 10D20000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x10D20000 0x1000>;
+ ranges = <0 0x10D20000 0x6000>;
+
+ cci_control0: slave-if at 1000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace-lite";
+ reg = <0x1000 0x1000>;
+ };
+
+ cci_control1: slave-if at 4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if at 5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+ };
+
+ clock: clock-controller at 10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
+
+ mct at 101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0xB00>;
+ interrupt-controller;
+ #interrups-cells = <1>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &combiner 23 3>,
+ <1 &combiner 23 4>,
+ <2 &combiner 25 2>,
+ <3 &combiner 25 3>,
+ <4 &gic 0 120 0>,
+ <5 &gic 0 121 0>,
+ <6 &gic 0 122 0>,
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
+ };
+ };
+
+ mmc_0: mmc at 12200000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12200000 0x1000>;
+ clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_1: mmc at 12210000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12210000 0x1000>;
+ clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ mmc_2: mmc at 12220000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x12220000 0x1000>;
+ clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ status = "disabled";
+ };
+
+ serial at 12C00000 {
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C10000 {
+ clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C20000 {
+ clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+ serial at 12C30000 {
+ clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
+
+};
--
1.8.1.5
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
` (3 preceding siblings ...)
2013-10-14 15:08 ` [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410 Vyacheslav Tyrtov
@ 2013-10-16 22:15 ` Kevin Hilman
2013-10-17 13:04 ` Aliaksei Katovich
4 siblings, 1 reply; 25+ messages in thread
From: Kevin Hilman @ 2013-10-16 22:15 UTC (permalink / raw)
To: linux-arm-kernel
Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
> The series of patches represent support of Exynos 5410 SoC
>
> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
>
> Patches add new platform description, support of clock controller,
> dual cluster support and device tree for Exynos 5410
>
> Has been build on v3.12-rc5.
> Has been tested on Exynos 5410 reference board (exynos_defconfig).
Has anyone tried this on the exynos5410 based odroid-xu yet?
I tried booting this on my recently arrived odroid-xu, but am not
getting it to boot.
I'm not yet terribly familiar with this SoC, what are the settings
needed for DEBUG_LL on this board?
Thanks,
Kevin
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
2013-10-14 15:08 ` [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support Vyacheslav Tyrtov
@ 2013-10-17 10:45 ` Daniel Lezcano
2013-10-25 10:06 ` Aliaksei Katovich
1 sibling, 0 replies; 25+ messages in thread
From: Daniel Lezcano @ 2013-10-17 10:45 UTC (permalink / raw)
To: linux-arm-kernel
On 10/14/2013 05:08 PM, Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
> This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
IIUC, the 5410 has a CCI-400 bug preventing to use the two clusters at
the same time. Right ? Could you explain how you fixed it ?
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> arch/arm/mach-exynos/Makefile | 2 +
> arch/arm/mach-exynos/edcs.c | 270 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 arch/arm/mach-exynos/edcs.c
>
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 5369615..ba6efdb 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
>
> obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
> obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
> +
> +obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
> diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
> new file mode 100644
> index 0000000..e304bd9
> --- /dev/null
> +++ b/arch/arm/mach-exynos/edcs.c
> @@ -0,0 +1,270 @@
> +/*
> + * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * EDCS(exynos dual cluster support) for Exynos5410 SoC.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +#include <linux/errno.h>
> +
> +#include <asm/mcpm.h>
> +#include <asm/proc-fns.h>
> +#include <asm/cacheflush.h>
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +
> +#include <linux/arm-cci.h>
> +#include <mach/regs-pmu.h>
> +
> +#define EDCS_CPUS_PER_CLUSTER 4
> +#define EDCS_CLUSTERS 2
> +
> +/* Exynos5410 power management registers */
> +#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION \
> + + ((_nr) * 0x80))
> +#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
> +#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
> +
> +#define REG_CPU_STATE_ADDR0 (S5P_VA_SYSRAM_NS + 0x28)
> +#define REG_CPU_STATE_ADDR(_nr) (REG_CPU_STATE_ADDR0 + \
> + _nr * EDCS_CPUS_PER_CLUSTER)
> +
> +static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +
> +static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
> +static int core_count[EDCS_CLUSTERS];
> +
> +static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
> + bool enable)
> +{
> + unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
> + int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
> +
> + if ((__raw_readl(EDCS_CORE_STATUS(offset)) & 0x3) != value)
> + __raw_writel(value, EDCS_CORE_CONFIGURATION(offset));
> +}
> +
> +static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + exynos_core_power_control(cpu, cluster, true);
> +}
> +
> +static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
> +{
> + exynos_core_power_control(cpu, cluster, false);
> +}
> +
> +void set_boot_flag(unsigned int cpu, unsigned int mode)
> +{
> + __raw_writel(mode, REG_CPU_STATE_ADDR(cpu));
> +}
> +
> +static int exynos_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> +
> + local_irq_disable();
> + arch_spin_lock(&edcs_lock);
> +
> + edcs_use_count[cpu][cluster]++;
> + if (edcs_use_count[cpu][cluster] == 1) {
> + ++core_count[cluster];
> + set_boot_flag(cpu, 0x2);
> + exynos_core_power_up(cpu, cluster);
> + } else if (edcs_use_count[cpu][cluster] != 2) {
> + /*
> + * The only possible values are:
> + * 0 = CPU down
> + * 1 = CPU (still) up
> + * 2 = CPU requested to be up before it had a chance
> + * to actually make itself down.
> + * Any other value is a bug.
> + */
> + BUG();
> + }
> +
> + arch_spin_unlock(&edcs_lock);
> + local_irq_enable();
> +
> + return 0;
> +}
> +static void exynos_power_down(void)
> +{
> + unsigned int mpidr, cpu, cluster;
> + bool last_man = false, skip_wfi = false;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> +
> + __mcpm_cpu_going_down(cpu, cluster);
> +
> + arch_spin_lock(&edcs_lock);
> + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> + edcs_use_count[cpu][cluster]--;
> + if (edcs_use_count[cpu][cluster] == 0) {
> + --core_count[cluster];
> + if (core_count[cluster] == 0)
> + last_man = true;
> + } else if (edcs_use_count[cpu][cluster] == 1) {
> + /*
> + * A power_up request went ahead of us.
> + * Even if we do not want to shut this CPU down,
> + * the caller expects a certain state as if the WFI
> + * was aborted. So let's continue with cache cleaning.
> + */
> + skip_wfi = true;
> + } else
> + BUG();
> +
> + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> + arch_spin_unlock(&edcs_lock);
> +
> + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
> + /*
> + * On the Cortex-A15 we need to disable
> + * L2 prefetching before flushing the cache.
> + */
> + asm volatile(
> + "mcr p15, 1, %0, c15, c0, 3\n\t"
> + "isb\n\t"
> + "dsb"
> + : : "r" (0x400));
> + }
> +
> + /*
> + * We need to disable and flush the whole (L1 and L2) cache.
> + * Let's do it in the safest possible way i.e. with
> + * no memory access within the following sequence
> + * including the stack.
> + *
> + * Note: fp is preserved to the stack explicitly prior doing
> + * this since adding it to the clobber list is incompatible
> + * with having CONFIG_FRAME_POINTER=y.
> + */
> + asm volatile(
> + "str fp, [sp, #-4]!\n\t"
> + "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
> + "bic r0, r0, #"__stringify(CR_C)"\n\t"
> + "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
> + "isb\n\t"
> + "bl v7_flush_dcache_all\n\t"
> + "clrex\n\t"
> + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
> + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
> + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
> + "isb\n\t"
> + "dsb\n\t"
> + "ldr fp, [sp], #4"
> + : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r9", "r10", "lr", "memory");
> +
> + cci_disable_port_by_cpu(mpidr);
> +
> + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> +
> + } else {
> + arch_spin_unlock(&edcs_lock);
> + /*
> + * We need to disable and flush only the L1 cache.
> + * Let's do it in the safest possible way as above.
> + */
> + asm volatile(
> + "str fp, [sp, #-4]!\n\t"
> + "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
> + "bic r0, r0, #"__stringify(CR_C)"\n\t"
> + "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
> + "isb\n\t"
> + "bl v7_flush_dcache_louis\n\t"
> + "clrex\n\t"
> + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
> + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
> + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
> + "isb\n\t"
> + "dsb\n\t"
> + "ldr fp, [sp], #4"
> + : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r9", "r10", "lr", "memory");
> +
> + }
> + __mcpm_cpu_down(cpu, cluster);
> +
> + if (!skip_wfi) {
> + exynos_core_power_down(cpu, cluster);
> + wfi();
> + }
> +}
I did not looked line by line but these functions looks very similar
than the tc2_pm.c's function. no ?
May be some code consolidation could be considered here.
Added Nico and Lorenzo in Cc.
Thanks
-- Daniel
> +static const struct mcpm_platform_ops exynos_power_ops = {
> + .power_up = exynos_power_up,
> + .power_down = exynos_power_down,
> +};
> +
> +static void __init edcs_data_init(void)
> +{
> + unsigned int mpidr, cpu, cluster;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> + edcs_use_count[cpu][cluster] = 1;
> + ++core_count[cluster];
> +}
> +
> +/*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + */
> +static void __naked edcs_power_up_setup(unsigned int affinity_level)
> +{
> + asm volatile ("\n"
> + "b cci_enable_port_for_self");
> +}
> +
> +static int __init edcs_init(void)
> +{
> + int ret;
> + struct device_node *node;
> +
> + node = of_find_compatible_node(NULL, NULL, "samsung,exynos5410");
> + if (!node)
> + return -ENODEV;
> +
> + if (!cci_probed())
> + return -ENODEV;
> +
> + /*
> + * Future entries into the kernel can now go
> + * through the cluster entry vectors.
> + */
> + __raw_writel(virt_to_phys(mcpm_entry_point),
> + S5P_VA_SYSRAM_NS + 0x1c);
> +
> + edcs_data_init();
> + mcpm_smp_set_ops();
> +
> + ret = mcpm_platform_register(&exynos_power_ops);
> + if (!ret) {
> + mcpm_sync_init(edcs_power_up_setup);
> + pr_info("EDCS power management initialized\n");
> + }
> + return ret;
> +}
> +
> +early_initcall(edcs_init);
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-16 22:15 ` [PATCH v2 0/4] Exynos 5410 Dual cluster support Kevin Hilman
@ 2013-10-17 13:04 ` Aliaksei Katovich
2013-10-17 13:51 ` Tarek Dakhran
` (2 more replies)
0 siblings, 3 replies; 25+ messages in thread
From: Aliaksei Katovich @ 2013-10-17 13:04 UTC (permalink / raw)
To: linux-arm-kernel
hi Kevin;
> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>
> > The series of patches represent support of Exynos 5410 SoC
> >
> > The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
> > Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
> >
> > Patches add new platform description, support of clock controller,
> > dual cluster support and device tree for Exynos 5410
> >
> > Has been build on v3.12-rc5.
> > Has been tested on Exynos 5410 reference board (exynos_defconfig).
>
> Has anyone tried this on the exynos5410 based odroid-xu yet?
>
> I tried booting this on my recently arrived odroid-xu, but am not
> getting it to boot.
I am able to boot my odroid-xu+e to busybox with these patches applied
against 3.12-rc5: exynos_defconfig and exynos5410-smdk5410.dtb were
used.
However there seem to be some issues with virq allocations, like this:
<snippet>
Starting kernel ...
[ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
[ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
[ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
[ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
[ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
[ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
)
[ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
[ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
[ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
[ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
[ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
[ 0.000000] ---[ end trace 1b75b31a2719edcd ]---
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/irq/irqdomain.c:278 irq_domain_associate+0x128/0x1a8()
[ 0.000000] error: virq337 is not allocated
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00004-g1cb405f #1
[ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
[ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
[ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
[ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
[ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
[ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
)
[ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
[ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
[ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
[ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
[ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
[ 0.000000] ---[ end trace 1b75b31a2719edce ]---
[ 0.000000] ------------[ cut here ]------------
</snippet>
You can check full boot log here http://sprunge.us/NKcU
--
Aliaksei
>
> I'm not yet terribly familiar with this SoC, what are the settings
> needed for DEBUG_LL on this board?
>
> Thanks,
>
> Kevin
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-17 13:04 ` Aliaksei Katovich
@ 2013-10-17 13:51 ` Tarek Dakhran
2013-10-17 14:24 ` Aliaksei Katovich
2013-10-17 14:02 ` Tarek Dakhran
2013-10-17 20:00 ` Kevin Hilman
2 siblings, 1 reply; 25+ messages in thread
From: Tarek Dakhran @ 2013-10-17 13:51 UTC (permalink / raw)
To: linux-arm-kernel
On 17.10.2013 17:04, Aliaksei Katovich wrote:
> hi Kevin;
>
>> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>>
>>> The series of patches represent support of Exynos 5410 SoC
>>>
>>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
>>> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
>>>
>>> Patches add new platform description, support of clock controller,
>>> dual cluster support and device tree for Exynos 5410
>>>
>>> Has been build on v3.12-rc5.
>>> Has been tested on Exynos 5410 reference board (exynos_defconfig).
>> Has anyone tried this on the exynos5410 based odroid-xu yet?
>>
>> I tried booting this on my recently arrived odroid-xu, but am not
>> getting it to boot.
> I am able to boot my odroid-xu+e to busybox with these patches applied
> against 3.12-rc5: exynos_defconfig and exynos5410-smdk5410.dtb were
> used.
>
> However there seem to be some issues with virq allocations, like this:
>
> <snippet>
> Starting kernel ...
>
> [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> )
> [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> [ 0.000000] ---[ end trace 1b75b31a2719edcd ]---
> [ 0.000000] ------------[ cut here ]------------
> [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/irq/irqdomain.c:278 irq_domain_associate+0x128/0x1a8()
> [ 0.000000] error: virq337 is not allocated
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00004-g1cb405f #1
> [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> )
> [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> [ 0.000000] ---[ end trace 1b75b31a2719edce ]---
> [ 0.000000] ------------[ cut here ]------------
> </snippet>
>
> You can check full boot log here http://sprunge.us/NKcU
>
> --
> Aliaksei
>
>> I'm not yet terribly familiar with this SoC, what are the settings
>> needed for DEBUG_LL on this board?
>>
>> Thanks,
>>
>> Kevin
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
This will be fixed in 3.13.
Now you can just change "irq_base = 160" to "irq_base = 256"
in "static int __init combiner_of_init(struct device_node *np, struct
device_node *parent)" function
in "drivers/irqchip/exynos-combiner.c"
Best regards,
Tarek Dakhran
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-17 13:04 ` Aliaksei Katovich
2013-10-17 13:51 ` Tarek Dakhran
@ 2013-10-17 14:02 ` Tarek Dakhran
2013-10-17 20:00 ` Kevin Hilman
2 siblings, 0 replies; 25+ messages in thread
From: Tarek Dakhran @ 2013-10-17 14:02 UTC (permalink / raw)
To: linux-arm-kernel
On 17.10.2013 17:04, Aliaksei Katovich wrote:
> hi Kevin;
>
>> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>>
>>> The series of patches represent support of Exynos 5410 SoC
>>>
>>> The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
>>> Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
>>>
>>> Patches add new platform description, support of clock controller,
>>> dual cluster support and device tree for Exynos 5410
>>>
>>> Has been build on v3.12-rc5.
>>> Has been tested on Exynos 5410 reference board (exynos_defconfig).
>> Has anyone tried this on the exynos5410 based odroid-xu yet?
>>
>> I tried booting this on my recently arrived odroid-xu, but am not
>> getting it to boot.
> I am able to boot my odroid-xu+e to busybox with these patches applied
> against 3.12-rc5: exynos_defconfig and exynos5410-smdk5410.dtb were
> used.
>
> However there seem to be some issues with virq allocations, like this:
>
> <snippet>
> Starting kernel ...
>
> [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> )
> [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> [ 0.000000] ---[ end trace 1b75b31a2719edcd ]---
> [ 0.000000] ------------[ cut here ]------------
> [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/irq/irqdomain.c:278 irq_domain_associate+0x128/0x1a8()
> [ 0.000000] error: virq337 is not allocated
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00004-g1cb405f #1
> [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> )
> [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> [ 0.000000] ---[ end trace 1b75b31a2719edce ]---
> [ 0.000000] ------------[ cut here ]------------
> </snippet>
>
> You can check full boot log here http://sprunge.us/NKcU
>
> --
> Aliaksei
>
>> I'm not yet terribly familiar with this SoC, what are the settings
>> needed for DEBUG_LL on this board?
>>
>> Thanks,
>>
>> Kevin
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
Also change NR_CPUS to 8 in kernel config, so you will get 8 cores
booted instead of 2.
Best regards,
Tarek Dakhran
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-17 13:51 ` Tarek Dakhran
@ 2013-10-17 14:24 ` Aliaksei Katovich
0 siblings, 0 replies; 25+ messages in thread
From: Aliaksei Katovich @ 2013-10-17 14:24 UTC (permalink / raw)
To: linux-arm-kernel
hi Tarek;
<skip>
> > However there seem to be some issues with virq allocations, like this:
> >
> > <snippet>
> > Starting kernel ...
> >
> > [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> > [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> > [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> > [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> > [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> > [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> > )
> > [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> > [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> > [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> > [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> > [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> > [ 0.000000] ---[ end trace 1b75b31a2719edcd ]---
> > [ 0.000000] ------------[ cut here ]------------
> > [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/irq/irqdomain.c:278 irq_domain_associate+0x128/0x1a8()
> > [ 0.000000] error: virq337 is not allocated
> > [ 0.000000] Modules linked in:
> > [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc5-00004-g1cb405f #1
> > [ 0.000000] [<c0014d48>] (unwind_backtrace+0x0/0xf8) from [<c00117d0>] (show_stack+0x10/0x14)
> > [ 0.000000] [<c00117d0>] (show_stack+0x10/0x14) from [<c0363488>] (dump_stack+0x6c/0xac)
> > [ 0.000000] [<c0363488>] (dump_stack+0x6c/0xac) from [<c001e330>] (warn_slowpath_common+0x64/0x88)
> > [ 0.000000] [<c001e330>] (warn_slowpath_common+0x64/0x88) from [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40)
> > [ 0.000000] [<c001e3e8>] (warn_slowpath_fmt+0x30/0x40) from [<c005a1b4>] (irq_domain_associate+0x128/0x1a8)
> > [ 0.000000] [<c005a1b4>] (irq_domain_associate+0x128/0x1a8) from [<c005a508>] (irq_domain_associate_many+0x30/0x3c
> > )
> > [ 0.000000] [<c005a508>] (irq_domain_associate_many+0x30/0x3c) from [<c005a768>] (irq_domain_add_simple+0x78/0x90)
> > [ 0.000000] [<c005a768>] (irq_domain_add_simple+0x78/0x90) from [<c04b044c>] (combiner_of_init+0xb4/0x198)
> > [ 0.000000] [<c04b044c>] (combiner_of_init+0xb4/0x198) from [<c04b6938>] (of_irq_init+0x278/0x2a0)
> > [ 0.000000] [<c04b6938>] (of_irq_init+0x278/0x2a0) from [<c049b8fc>] (start_kernel+0x18c/0x384)
> > [ 0.000000] [<c049b8fc>] (start_kernel+0x18c/0x384) from [<40008074>] (0x40008074)
> > [ 0.000000] ---[ end trace 1b75b31a2719edce ]---
> > [ 0.000000] ------------[ cut here ]------------
> > </snippet>
> This will be fixed in 3.13.
>
> Now you can just change "irq_base = 160" to "irq_base = 256"
> in "static int __init combiner_of_init(struct device_node *np, struct
> device_node *parent)" function
> in "drivers/irqchip/exynos-combiner.c"
Thanks, this works for me!
--
Aliaksei
>
> Best regards,
> Tarek Dakhran
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
2013-10-17 13:04 ` Aliaksei Katovich
2013-10-17 13:51 ` Tarek Dakhran
2013-10-17 14:02 ` Tarek Dakhran
@ 2013-10-17 20:00 ` Kevin Hilman
[not found] ` <CAGc3s_cbCgdPdbCPF2XN+p-O5RfM-4pNZT49=_4MOVy=Lz8d=Q@mail.gmail.com>
2 siblings, 1 reply; 25+ messages in thread
From: Kevin Hilman @ 2013-10-17 20:00 UTC (permalink / raw)
To: linux-arm-kernel
Aliaksei Katovich <aliaksei.katovich@gmail.com> writes:
> hi Kevin;
>
>> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>>
>> > The series of patches represent support of Exynos 5410 SoC
>> >
>> > The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture.
>> > Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
>> >
>> > Patches add new platform description, support of clock controller,
>> > dual cluster support and device tree for Exynos 5410
>> >
>> > Has been build on v3.12-rc5.
>> > Has been tested on Exynos 5410 reference board (exynos_defconfig).
>>
>> Has anyone tried this on the exynos5410 based odroid-xu yet?
>>
>> I tried booting this on my recently arrived odroid-xu, but am not
>> getting it to boot.
>
> I am able to boot my odroid-xu+e to busybox with these patches applied
> against 3.12-rc5: exynos_defconfig and exynos5410-smdk5410.dtb were
> used.
>
> However there seem to be some issues with virq allocations, like this:
Ah, I've seen the same thing, but for me it doesn't boot reliably.
Sometimes there's an immediate fault like this[1], and once in a rare
while, it starts to boot and I see the same virq errors.
Curious what you guys are using for boot loaders. I found some
pre-build u-boot binaries along with the necessary BL1/2 binary blobs in
the hardkernel kernel repo: https://github.com/hardkernel/linux.git
branch: origin/odroidxu-3.4.y
path: tools/hardkernel/u-boot-pre-built
Unfortunatly, that u-boot doesn't have usb networking support built in
so I couln't use u-boot to tftp the kernel, so I was able to use fasboot
to load the kernel/ramdisk, but it's very flaky.
Do you have an pointers of where to get a known working bootloader.
Ideally, a u-boot with networking/tftp support would be ideal.
Thanks,
Kevin
[1]
USB cable Connected![0x4]
Starting download of 10008576 bytes
.........
downloading of 10008576 bytes finished
Kernel size: 00296bc5
Ramdisk size: 006f3c00
Booting kernel..
## Booting kernel from Legacy Image at 40008000 ...
Image Name: Linux
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2714501 Bytes = 2.6 MiB
Load Address: 40008000
Entry Point: 40008000
Verifying Checksum ... OK
XIP Kernel Image ... OK
OK
Starting kernel ...
undefined instruction
pc : [<4000800c>] lr : [<bfc65df4>]
sp : bfb5bbc8 ip : 00000000 fp : 00001251
r10: 00000000 r9 : 00000000 r8 : bfb5bf30
r7 : 00000000 r6 : 00000000 r5 : 40008000 r4 : bfcabac0
r3 : bfb5bfa8 r2 : 40000100 r1 : 00001251 r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
emmc resetting ...
resetting ...
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-10-14 15:08 ` [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
@ 2013-10-22 9:44 ` Mike Turquette
2013-11-01 15:53 ` Mauro Ribeiro
2013-11-01 16:58 ` Tomasz Figa
1 sibling, 1 reply; 25+ messages in thread
From: Mike Turquette @ 2013-10-22 9:44 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
Looks good to me. Any objections for me to take this through the clk
tree?
Regards,
Mike
> ---
> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 251 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5410.h | 175 ++++++++++++++
> 4 files changed, 464 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 0000000..a462da231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,37 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "samsung,exynos5410-clock"
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos5410.h header and can be used in device
> +tree sources.
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> + clock: clock-controller at 0x10010000 {
> + compatible = "samsung,exynos5410-clock";
> + reg = <0x10010000 0x30000>;
> + #clock-cells = <1>;
> + };
> +
> +Example 2: UART controller node that consumes the clock generated by the clock
> + controller. Refer to the standard clock bindings for information
> + about 'clocks' and 'clock-names' property.
> +
> + serial at 12C20000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C00000 0x100>;
> + interrupts = <0 51 0>;
> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + };
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 3413380..5a446ca 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -5,6 +5,7 @@
> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
> new file mode 100644
> index 0000000..c5eba08
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -0,0 +1,251 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Exynos5410 SoC.
> +*/
> +
> +#include <dt-bindings/clock/exynos5410.h>
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include "clk.h"
> +
> +#define APLL_LOCK 0x0
> +#define APLL_CON0 0x100
> +#define CPLL_LOCK 0x10020
> +#define CPLL_CON0 0x10120
> +#define MPLL_LOCK 0x4000
> +#define MPLL_CON0 0x4100
> +#define BPLL_LOCK 0x20010
> +#define BPLL_CON0 0x20110
> +#define KPLL_LOCK 0x28000
> +#define KPLL_CON0 0x28100
> +
> +#define SRC_CPU 0x200
> +#define DIV_CPU0 0x500
> +#define SRC_CPERI1 0x4204
> +#define DIV_TOP0 0x10510
> +#define DIV_TOP1 0x10514
> +#define DIV_FSYS1 0x1054c
> +#define DIV_FSYS2 0x10550
> +#define DIV_PERIC0 0x10558
> +#define SRC_TOP0 0x10210
> +#define SRC_TOP1 0x10214
> +#define SRC_TOP2 0x10218
> +#define SRC_FSYS 0x10244
> +#define SRC_PERIC0 0x10250
> +#define SRC_MASK_FSYS 0x10340
> +#define SRC_MASK_PERIC0 0x10350
> +#define GATE_BUS_FSYS0 0x10740
> +#define GATE_IP_FSYS 0x10944
> +#define GATE_IP_PERIC 0x10950
> +#define GATE_IP_PERIS 0x10960
> +#define SRC_CDREX 0x20200
> +#define SRC_KFC 0x28200
> +#define DIV_KFC0 0x28500
> +
> +/* list of PLLs */
> +enum exynos5410_plls {
> + apll, cpll, mpll,
> + bpll, kpll,
> + nr_plls /* number of PLLs */
> +};
> +
> +/*
> + * list of controller registers to be saved and restored during a
> + * suspend/resume cycle.
> + */
> +static unsigned long exynos5410_clk_regs[] __initdata = {
> + SRC_CPU,
> + DIV_CPU0,
> + SRC_CPERI1,
> + DIV_TOP0,
> + DIV_TOP1,
> + DIV_FSYS1,
> + DIV_FSYS2,
> + DIV_PERIC0,
> + SRC_TOP0,
> + SRC_TOP1,
> + SRC_TOP2,
> + SRC_FSYS,
> + SRC_PERIC0,
> + SRC_MASK_FSYS,
> + SRC_MASK_PERIC0,
> + GATE_BUS_FSYS0,
> + GATE_IP_FSYS,
> + GATE_IP_PERIC,
> + GATE_IP_PERIS,
> + SRC_CDREX,
> + SRC_KFC,
> + DIV_KFC0,
> +};
> +
> +/* list of all parent clocks */
> +PNAME(apll_p) = { "fin_pll", "fout_apll", };
> +PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
> +PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
> +PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
> +PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
> +
> +PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
> +PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
> +
> +PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
> +PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
> +PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
> +
> +PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
> + "none", "none", "sclk_mpll_bpll",
> + "none", "none", "sclk_cpll" };
> +
> +/* fixed rate clocks generated outside the soc */
> +static struct samsung_fixed_rate_clock exynos5410_frt_ext_clks[] __initdata = {
> + FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
> +};
> +
> +static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
> + MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
> + MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
> +
> + MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
> + MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
> +
> + MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
> + MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
> +
> + MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
> + MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
> +
> + MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
> +
> + MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
> +
> + MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
> + MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
> + MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
> +
> + MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
> + MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
> + MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
> +
> + MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
> + MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
> +};
> +
> +static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
> + DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> + DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
> +
> + DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
> + DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
> + DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
> + DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
> +
> + DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
> + DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
> + DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
> +
> + DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
> + DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
> +
> + DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
> + DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
> + DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
> +
> + DIV_F(0, "div_mmc_pre0", "div_mmc0",
> + DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
> + DIV_F(0, "div_mmc_pre1", "div_mmc1",
> + DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
> + DIV_F(0, "div_mmc_pre2", "div_mmc2",
> + DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
> +
> + DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
> + DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
> + DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
> + DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
> +
> + DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> + DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
> +};
> +
> +static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
> + GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
> +
> + GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
> + SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
> + SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
> + SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
> +
> + GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
> + GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
> + GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
> +
> + GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
> + GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
> + GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
> +
> + GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> + SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> + SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
> +};
> +
> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
> + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> + APLL_CON0, NULL),
> + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
> + CPLL_CON0, NULL),
> + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
> + MPLL_CON0, NULL),
> + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
> + BPLL_CON0, NULL),
> + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
> + KPLL_CON0, NULL),
> +};
> +
> +static struct of_device_id ext_clk_match[] __initdata = {
> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
> + { },
> +};
> +
> +/* register exynos5410 clocks */
> +static void __init exynos5410_clk_init(struct device_node *np)
> +{
> + void __iomem *reg_base;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base)
> + panic("%s: failed to map registers\n", __func__);
> +
> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
> + exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
> + NULL, 0);
> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
> + ARRAY_SIZE(exynos5410_frt_ext_clks),
> + ext_clk_match);
> + samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
> + reg_base);
> +
> + samsung_clk_register_mux(exynos5410_mux_clks,
> + ARRAY_SIZE(exynos5410_mux_clks));
> + samsung_clk_register_div(exynos5410_div_clks,
> + ARRAY_SIZE(exynos5410_div_clks));
> + samsung_clk_register_gate(exynos5410_gate_clks,
> + ARRAY_SIZE(exynos5410_gate_clks));
> +
> + pr_debug("Exynos5410: clock setup completed.\n");
> +}
> +CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> new file mode 100644
> index 0000000..9b4a58b
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -0,0 +1,175 @@
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
> +
> +/* core clocks */
> +#define CLK_FIN_PLL 1
> +#define CLK_FOUT_APLL 2
> +#define CLK_FOUT_CPLL 3
> +#define CLK_FOUT_DPLL 4
> +#define CLK_FOUT_EPLL 5
> +#define CLK_FOUT_RPLL 6
> +#define CLK_FOUT_IPLL 7
> +#define CLK_FOUT_SPLL 8
> +#define CLK_FOUT_VPLL 9
> +#define CLK_FOUT_MPLL 10
> +#define CLK_FOUT_BPLL 11
> +#define CLK_FOUT_KPLL 12
> +
> +/* gate for special clocks (sclk) */
> +#define CLK_SCLK_UART0 128
> +#define CLK_SCLK_UART1 129
> +#define CLK_SCLK_UART2 130
> +#define CLK_SCLK_UART3 131
> +#define CLK_SCLK_MMC0 132
> +#define CLK_SCLK_MMC1 133
> +#define CLK_SCLK_MMC2 134
> +#define CLK_SCLK_SPI0 135
> +#define CLK_SCLK_SPI1 136
> +#define CLK_SCLK_SPI2 137
> +#define CLK_SCLK_I2S1 138
> +#define CLK_SCLK_I2S2 139
> +#define CLK_SCLK_PCM1 140
> +#define CLK_SCLK_PCM2 141
> +#define CLK_SCLK_SPDIF 142
> +#define CLK_SCLK_HDMI 143
> +#define CLK_SCLK_PIXEL 144
> +#define CLK_SCLK_DP1 145
> +#define CLK_SCLK_MIPI1 146
> +#define CLK_SCLK_FIMD1 147
> +#define CLK_SCLK_MAUDIO0 148
> +#define CLK_SCLK_MAUPCM0 149
> +#define CLK_SCLK_USBD300 150
> +#define CLK_SCLK_USBD301 151
> +#define CLK_SCLK_USBPHY300 152
> +#define CLK_SCLK_USBPHY301 153
> +#define CLK_SCLK_UNIPRO 154
> +#define CLK_SCLK_PWM 155
> +#define CLK_SCLK_GSCL_WA 156
> +#define CLK_SCLK_GSCL_WB 157
> +#define CLK_SCLK_HDMIPHY 158
> +
> +/* gate clocks */
> +#define CLK_ACLK66_PERIC 256
> +#define CLK_UART0 257
> +#define CLK_UART1 258
> +#define CLK_UART2 259
> +#define CLK_UART3 260
> +#define CLK_I2C0 261
> +#define CLK_I2C1 262
> +#define CLK_I2C2 263
> +#define CLK_I2C3 264
> +#define CLK_I2C4 265
> +#define CLK_I2C5 266
> +#define CLK_I2C6 267
> +#define CLK_I2C7 268
> +#define CLK_I2C_HDMI 269
> +#define CLK_TSADC 270
> +#define CLK_SPI0 271
> +#define CLK_SPI1 272
> +#define CLK_SPI2 273
> +#define CLK_KEYIF 274
> +#define CLK_I2S1 275
> +#define CLK_I2S2 276
> +#define CLK_PCM1 277
> +#define CLK_PCM2 278
> +#define CLK_PWM 279
> +#define CLK_SPDIF 280
> +#define CLK_I2C8 281
> +#define CLK_I2C9 282
> +#define CLK_I2C10 283
> +#define CLK_ACLK66_PSGEN 300
> +#define CLK_CHIPID 301
> +#define CLK_SYSREG 302
> +#define CLK_TZPC0 303
> +#define CLK_TZPC1 304
> +#define CLK_TZPC2 305
> +#define CLK_TZPC3 306
> +#define CLK_TZPC4 307
> +#define CLK_TZPC5 308
> +#define CLK_TZPC6 309
> +#define CLK_TZPC7 310
> +#define CLK_TZPC8 311
> +#define CLK_TZPC9 312
> +#define CLK_HDMI_CEC 313
> +#define CLK_SECKEY 314
> +#define CLK_MCT 315
> +#define CLK_WDT 316
> +#define CLK_RTC 317
> +#define CLK_TMU 318
> +#define CLK_TMU_GPU 319
> +#define CLK_PCLK66_GPIO 330
> +#define CLK_ACLK200_FSYS2 350
> +#define CLK_MMC0 351
> +#define CLK_MMC1 352
> +#define CLK_MMC2 353
> +#define CLK_SROMC 354
> +#define CLK_UFS 355
> +#define CLK_ACLK200_FSYS 360
> +#define CLK_TSI 361
> +#define CLK_PDMA0 362
> +#define CLK_PDMA1 363
> +#define CLK_RTIC 364
> +#define CLK_USBH20 365
> +#define CLK_USBD300 366
> +#define CLK_USBD301 367
> +#define CLK_ACLK400_MSCL 380
> +#define CLK_MSCL0 381
> +#define CLK_MSCL1 382
> +#define CLK_MSCL2 383
> +#define CLK_SMMU_MSCL0 384
> +#define CLK_SMMU_MSCL1 385
> +#define CLK_SMMU_MSCL2 386
> +#define CLK_ACLK333 400
> +#define CLK_MFC 401
> +#define CLK_SMMU_MFCL 402
> +#define CLK_SMMU_MFCR 403
> +#define CLK_ACLK200_DISP1 410
> +#define CLK_DSIM1 411
> +#define CLK_DP1 412
> +#define CLK_HDMI 413
> +#define CLK_ACLK300_DISP1 420
> +#define CLK_FIMD1 421
> +#define CLK_SMMU_FIMD1 422
> +#define CLK_ACLK166 430
> +#define CLK_MIXER 431
> +#define CLK_ACLK266 440
> +#define CLK_ROTATOR 441
> +#define CLK_MDMA1 442
> +#define CLK_SMMU_ROTATOR 443
> +#define CLK_SMMU_MDMA1 444
> +#define CLK_ACLK300_JPEG 450
> +#define CLK_JPEG 451
> +#define CLK_JPEG2 452
> +#define CLK_SMMU_JPEG 453
> +#define CLK_ACLK300_GSCL 460
> +#define CLK_SMMU_GSCL0 461
> +#define CLK_SMMU_GSCL1 462
> +#define CLK_GSCL_WA 463
> +#define CLK_GSCL_WB 464
> +#define CLK_GSCL0 465
> +#define CLK_GSCL1 466
> +#define CLK_CLK_3AA 467
> +#define CLK_ACLK266_G2D 470
> +#define CLK_SSS 471
> +#define CLK_SLIM_SSS 472
> +#define CLK_MDMA0 473
> +#define CLK_ACLK333_G2D 480
> +#define CLK_G2D 481
> +#define CLK_ACLK333_432_GSCL 490
> +#define CLK_SMMU_3AA 491
> +#define CLK_SMMU_FIMCL0 492
> +#define CLK_SMMU_FIMCL1 493
> +#define CLK_SMMU_FIMCL3 494
> +#define CLK_FIMC_LITE3 495
> +#define CLK_ACLK_G3D 500
> +#define CLK_G3D 501
> +#define CLK_SMMU_MIXER 502
> +
> +/* mux clocks */
> +#define CLK_MOUT_HDMI 640
> +
> +/* divider clocks */
> +#define CLK_DOUT_PIXEL 768
> +#define CLK_NR_CLKS 769
> +
> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
> --
> 1.8.1.5
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
2013-10-14 15:08 ` [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support Vyacheslav Tyrtov
2013-10-17 10:45 ` Daniel Lezcano
@ 2013-10-25 10:06 ` Aliaksei Katovich
2013-11-04 10:42 ` Alexei Colin
1 sibling, 1 reply; 25+ messages in thread
From: Aliaksei Katovich @ 2013-10-25 10:06 UTC (permalink / raw)
To: linux-arm-kernel
hi Vyacheslav;
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
> This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> arch/arm/mach-exynos/Makefile | 2 +
> arch/arm/mach-exynos/edcs.c | 270 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 arch/arm/mach-exynos/edcs.c
>
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 5369615..ba6efdb 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
>
> obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
> obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
> +
> +obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
> diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
> new file mode 100644
> index 0000000..e304bd9
> --- /dev/null
> +++ b/arch/arm/mach-exynos/edcs.c
> @@ -0,0 +1,270 @@
> +/*
> + * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * EDCS(exynos dual cluster support) for Exynos5410 SoC.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +#include <linux/errno.h>
> +
> +#include <asm/mcpm.h>
> +#include <asm/proc-fns.h>
> +#include <asm/cacheflush.h>
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +
> +#include <linux/arm-cci.h>
> +#include <mach/regs-pmu.h>
> +
> +#define EDCS_CPUS_PER_CLUSTER 4
> +#define EDCS_CLUSTERS 2
> +
> +/* Exynos5410 power management registers */
> +#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION \
> + + ((_nr) * 0x80))
> +#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
> +#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
> +
> +#define REG_CPU_STATE_ADDR0 (S5P_VA_SYSRAM_NS + 0x28)
> +#define REG_CPU_STATE_ADDR(_nr) (REG_CPU_STATE_ADDR0 + \
> + _nr * EDCS_CPUS_PER_CLUSTER)
> +
> +static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +
> +static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
> +static int core_count[EDCS_CLUSTERS];
> +
> +static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
> + bool enable)
> +{
> + unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
> + int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
> +
> + if ((__raw_readl(EDCS_CORE_STATUS(offset)) & 0x3) != value)
> + __raw_writel(value, EDCS_CORE_CONFIGURATION(offset));
> +}
> +
> +static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + exynos_core_power_control(cpu, cluster, true);
> +}
> +
> +static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
> +{
> + exynos_core_power_control(cpu, cluster, false);
> +}
> +
> +void set_boot_flag(unsigned int cpu, unsigned int mode)
> +{
> + __raw_writel(mode, REG_CPU_STATE_ADDR(cpu));
> +}
> +
> +static int exynos_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> +
> + local_irq_disable();
> + arch_spin_lock(&edcs_lock);
> +
> + edcs_use_count[cpu][cluster]++;
> + if (edcs_use_count[cpu][cluster] == 1) {
> + ++core_count[cluster];
> + set_boot_flag(cpu, 0x2);
> + exynos_core_power_up(cpu, cluster);
> + } else if (edcs_use_count[cpu][cluster] != 2) {
> + /*
> + * The only possible values are:
> + * 0 = CPU down
> + * 1 = CPU (still) up
> + * 2 = CPU requested to be up before it had a chance
> + * to actually make itself down.
> + * Any other value is a bug.
> + */
> + BUG();
> + }
> +
> + arch_spin_unlock(&edcs_lock);
> + local_irq_enable();
> +
> + return 0;
> +}
> +static void exynos_power_down(void)
> +{
> + unsigned int mpidr, cpu, cluster;
> + bool last_man = false, skip_wfi = false;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> +
> + __mcpm_cpu_going_down(cpu, cluster);
> +
> + arch_spin_lock(&edcs_lock);
> + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> + edcs_use_count[cpu][cluster]--;
> + if (edcs_use_count[cpu][cluster] == 0) {
> + --core_count[cluster];
> + if (core_count[cluster] == 0)
> + last_man = true;
> + } else if (edcs_use_count[cpu][cluster] == 1) {
> + /*
> + * A power_up request went ahead of us.
> + * Even if we do not want to shut this CPU down,
> + * the caller expects a certain state as if the WFI
> + * was aborted. So let's continue with cache cleaning.
> + */
> + skip_wfi = true;
> + } else
> + BUG();
> +
> + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> + arch_spin_unlock(&edcs_lock);
> +
> + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
> + /*
> + * On the Cortex-A15 we need to disable
> + * L2 prefetching before flushing the cache.
> + */
> + asm volatile(
> + "mcr p15, 1, %0, c15, c0, 3\n\t"
> + "isb\n\t"
> + "dsb"
> + : : "r" (0x400));
> + }
> +
> + /*
> + * We need to disable and flush the whole (L1 and L2) cache.
> + * Let's do it in the safest possible way i.e. with
> + * no memory access within the following sequence
> + * including the stack.
> + *
> + * Note: fp is preserved to the stack explicitly prior doing
> + * this since adding it to the clobber list is incompatible
> + * with having CONFIG_FRAME_POINTER=y.
> + */
> + asm volatile(
> + "str fp, [sp, #-4]!\n\t"
> + "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
> + "bic r0, r0, #"__stringify(CR_C)"\n\t"
> + "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
> + "isb\n\t"
> + "bl v7_flush_dcache_all\n\t"
> + "clrex\n\t"
> + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
> + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
> + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
> + "isb\n\t"
> + "dsb\n\t"
> + "ldr fp, [sp], #4"
> + : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r9", "r10", "lr", "memory");
> +
> + cci_disable_port_by_cpu(mpidr);
> +
> + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> +
> + } else {
> + arch_spin_unlock(&edcs_lock);
> + /*
> + * We need to disable and flush only the L1 cache.
> + * Let's do it in the safest possible way as above.
> + */
> + asm volatile(
> + "str fp, [sp, #-4]!\n\t"
> + "mrc p15, 0, r0, c1, c0, 0 @ get CR\n\t"
> + "bic r0, r0, #"__stringify(CR_C)"\n\t"
> + "mcr p15, 0, r0, c1, c0, 0 @ set CR\n\t"
> + "isb\n\t"
> + "bl v7_flush_dcache_louis\n\t"
> + "clrex\n\t"
> + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR\n\t"
> + "bic r0, r0, #(1 << 6) @ disable local coherency\n\t"
> + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR\n\t"
> + "isb\n\t"
> + "dsb\n\t"
> + "ldr fp, [sp], #4"
> + : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r9", "r10", "lr", "memory");
> +
> + }
> + __mcpm_cpu_down(cpu, cluster);
> +
> + if (!skip_wfi) {
> + exynos_core_power_down(cpu, cluster);
> + wfi();
> + }
> +}
> +
> +static const struct mcpm_platform_ops exynos_power_ops = {
> + .power_up = exynos_power_up,
> + .power_down = exynos_power_down,
> +};
> +
> +static void __init edcs_data_init(void)
> +{
> + unsigned int mpidr, cpu, cluster;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
> + edcs_use_count[cpu][cluster] = 1;
> + ++core_count[cluster];
> +}
> +
> +/*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + */
> +static void __naked edcs_power_up_setup(unsigned int affinity_level)
> +{
> + asm volatile ("\n"
> + "b cci_enable_port_for_self");
> +}
This code breaks odroid-xu boot with NR_CPUS set to 8. Kernel panics
like this:
%< -----------------------------------------------------------------------
[ 5.315000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 5.320000] Freeing unused kernel memory: 216K (c049b000 - c04d1000)
[ 5.325000] Unhandled fault: imprecise external abort (0x1406)@0x00000000
[ 5.340000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
[ 5.340000]
[ 5.345000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 200000Hz, actual 200000HZ div = 250)
[ 5.355000] CPU: 3 PID: 1 Comm: init Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
[ 5.365000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
[ 5.370000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
[ 5.380000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 196079Hz, actual 196078HZ div = 255)
[ 5.390000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c03609fc>] (panic+0x90/0x1e8)
[ 5.395000] [<c03609fc>] (panic+0x90/0x1e8) from [<c002048c>] (do_exit+0x780/0x834)
[ 5.405000] [<c002048c>] (do_exit+0x780/0x834) from [<c002062c>] (do_group_exit+0x3c/0xb0)
[ 5.410000] [<c002062c>] (do_group_exit+0x3c/0xb0) from [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534)
[ 5.420000] [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534) from [<c0010d08>] (do_signal+0x100/0x40c)
[ 5.430000] [<c0010d08>] (do_signal+0x100/0x40c) from [<c0011348>] (do_work_pending+0x68/0xa8)
[ 5.430000] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 50000000Hz, actual 50000000HZ div = 1)
[ 5.430000] mmc1: new high speed SDHC card at address b368
[ 5.435000] mmcblk0: mmc1:b368 USD 14.9 GiB
[ 5.440000] mmcblk0: p1 p2 p3 < p5 p6 p7 >
[ 5.455000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz, actual 400000HZ div = 125)
[ 5.475000] [<c0011348>] (do_work_pending+0x68/0xa8) from [<c000e420>] (work_pending+0xc/0x20)
[ 5.480000] CPU1: stopping
[ 5.480000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
[ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
[ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
[ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
[ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
[ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
[ 5.480000] Exception stack(0xef0a7f88 to 0xef0a7fd0)
[ 5.480000] 7f80: 00000001 00000000 008d20ff 00000001 00000000 00000000
[ 5.480000] 7fa0: c04d07a0 60000113 010da000 412fc0f3 c15aa7a0 00000000 00000001 ef0a7fd0
[ 5.480000] 7fc0: c0072d74 c0072d78 20000113 ffffffff
[ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c0072d78>] (rcu_idle_exit+0x68/0xb8)
[ 5.480000] [<c0072d78>] (rcu_idle_exit+0x68/0xb8) from [<c00550a4>] (cpu_startup_entry+0x6c/0x148)
[ 5.480000] [<c00550a4>] (cpu_startup_entry+0x6c/0x148) from [<400085c4>] (0x400085c4)
[ 5.480000] CPU0: stopping
[ 5.480000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
[ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
[ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
[ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
[ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
[ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
[ 5.480000] Exception stack(0xc04d3f70 to 0xc04d3fb8)
[ 5.480000] SMP: failed to stop secondary CPUs
[ 5.480000] 3f60: 00000000 00000000 00002190 00000000
[ 5.480000] 3f80: c04d2000 c050a88f 00000001 c050a88f c04da44c 412fc0f3 c036a960 00000000
[ 5.480000] 3fa0: 00000020 c04d3fb8 c000f5d4 c000f5d8 60000113 ffffffff
[ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
[ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
[ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<c049ba9c>] (start_kernel+0x32c/0x384)
[ 5.480000] CPU2: stopping
[ 5.480000] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
[ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
[ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
[ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
[ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
[ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
[ 5.480000] Exception stack(0xef0a9fa0 to 0xef0a9fe8)
[ 5.480000] 9fa0: 00000002 00000000 008e4858 00000000 ef0a8000 c050a88f 00000001 c050a88f
[ 5.480000] 9fc0: c04da44c 412fc0f3 c036a960 00000000 00000001 ef0a9fe8 c000f5d4 c000f5d8
[ 5.480000] 9fe0: 60000113 ffffffff
[ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
[ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
[ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<400085c4>] (0x400085c4)
%< -----------------------------------------------------------------------
I checked arch/arm/mach-vexpress/tc2_pm.c to see how CCI is enabled
there an realized that you should follow same pattern, i.e.:
asm volatile (" \n"
" cmp r0, #1 \n"
" bxne lr \n"
" b cci_enable_port_for_self ");
In this case only one cluster (4 LITTLE cores for Exynos5410) will be
initialized@boot time. And no panic.
--
Aliaksei
> +
> +static int __init edcs_init(void)
> +{
> + int ret;
> + struct device_node *node;
> +
> + node = of_find_compatible_node(NULL, NULL, "samsung,exynos5410");
> + if (!node)
> + return -ENODEV;
> +
> + if (!cci_probed())
> + return -ENODEV;
> +
> + /*
> + * Future entries into the kernel can now go
> + * through the cluster entry vectors.
> + */
> + __raw_writel(virt_to_phys(mcpm_entry_point),
> + S5P_VA_SYSRAM_NS + 0x1c);
> +
> + edcs_data_init();
> + mcpm_smp_set_ops();
> +
> + ret = mcpm_platform_register(&exynos_power_ops);
> + if (!ret) {
> + mcpm_sync_init(edcs_power_up_setup);
> + pr_info("EDCS power management initialized\n");
> + }
> + return ret;
> +}
> +
> +early_initcall(edcs_init);
> --
> 1.8.1.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 0/4] Exynos 5410 Dual cluster support
[not found] ` <CAGc3s_cbCgdPdbCPF2XN+p-O5RfM-4pNZT49=_4MOVy=Lz8d=Q@mail.gmail.com>
@ 2013-10-30 23:57 ` Kevin Hilman
0 siblings, 0 replies; 25+ messages in thread
From: Kevin Hilman @ 2013-10-30 23:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mauro,
Mauro Ribeiro <mdrjr0@gmail.com> writes:
> Kevin,
>
> https://github.com/hardkernel/u-boot/tree/odroid-v2012.07
Yes, this is the one I'm using, but USB networking doesn't seem to work
with that. Do you have USB networking working with that u-boot? If so,
what changes to the config did you make?
Kevin
>
> On Thu, Oct 17, 2013 at 5:00 PM, Kevin Hilman <khilman@linaro.org> wrote:
>
>> Aliaksei Katovich <aliaksei.katovich@gmail.com> writes:
>>
>> > hi Kevin;
>> >
>> >> Vyacheslav Tyrtov <v.tyrtov@samsung.com> writes:
>> >>
>> >> > The series of patches represent support of Exynos 5410 SoC
>> >> >
>> >> > The Exynos 5410 is the first Samsung SoC based on bigLITTLE
>> architecture.
>> >> > Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same
>> time
>> >> >
>> >> > Patches add new platform description, support of clock controller,
>> >> > dual cluster support and device tree for Exynos 5410
>> >> >
>> >> > Has been build on v3.12-rc5.
>> >> > Has been tested on Exynos 5410 reference board (exynos_defconfig).
>> >>
>> >> Has anyone tried this on the exynos5410 based odroid-xu yet?
>> >>
>> >> I tried booting this on my recently arrived odroid-xu, but am not
>> >> getting it to boot.
>> >
>> > I am able to boot my odroid-xu+e to busybox with these patches
>> applied
>> > against 3.12-rc5: exynos_defconfig and exynos5410-smdk5410.dtb were
>> > used.
>> >
>> > However there seem to be some issues with virq allocations, like
>> this:
>>
>> Ah, I've seen the same thing, but for me it doesn't boot reliably.
>> Sometimes there's an immediate fault like this[1], and once in a rare
>> while, it starts to boot and I see the same virq errors.
>>
>> Curious what you guys are using for boot loaders. I found some
>> pre-build u-boot binaries along with the necessary BL1/2 binary blobs in
>> the hardkernel kernel repo: https://github.com/hardkernel/linux.git
>> branch: origin/odroidxu-3.4.y
>> path: tools/hardkernel/u-boot-pre-built
>>
>> Unfortunatly, that u-boot doesn't have usb networking support built in
>> so I couln't use u-boot to tftp the kernel, so I was able to use fasboot
>> to load the kernel/ramdisk, but it's very flaky.
>>
>> Do you have an pointers of where to get a known working bootloader.
>> Ideally, a u-boot with networking/tftp support would be ideal.
>>
>> Thanks,
>>
>> Kevin
>>
>> [1]
>> USB cable Connected![0x4]
>> Starting download of 10008576 bytes
>> .........
>> downloading of 10008576 bytes finished
>> Kernel size: 00296bc5
>> Ramdisk size: 006f3c00
>> Booting kernel..
>> ## Booting kernel from Legacy Image at 40008000 ...
>> Image Name: Linux
>> Image Type: ARM Linux Kernel Image (uncompressed)
>> Data Size: 2714501 Bytes = 2.6 MiB
>> Load Address: 40008000
>> Entry Point: 40008000
>> Verifying Checksum ... OK
>> XIP Kernel Image ... OK
>> OK
>>
>> Starting kernel ...
>>
>> undefined instruction
>> pc : [<4000800c>] lr : [<bfc65df4>]
>> sp : bfb5bbc8 ip : 00000000 fp : 00001251
>> r10: 00000000 r9 : 00000000 r8 : bfb5bf30
>> r7 : 00000000 r6 : 00000000 r5 : 40008000 r4 : bfcabac0
>> r3 : bfb5bfa8 r2 : 40000100 r1 : 00001251 r0 : 00000000
>> Flags: nZCv IRQs off FIQs off Mode SVC_32
>> Resetting CPU ...
>>
>> emmc resetting ...
>> resetting ...
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
>> linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-10-22 9:44 ` Mike Turquette
@ 2013-11-01 15:53 ` Mauro Ribeiro
2013-11-01 16:25 ` Mauro Ribeiro
0 siblings, 1 reply; 25+ messages in thread
From: Mauro Ribeiro @ 2013-11-01 15:53 UTC (permalink / raw)
To: linux-arm-kernel
Is the PLL35xx driver compatible with the ones used on 5410?
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
It registers all the PLL's with the same PLL. While the manual says
others PLL names.
Regards,
Mauro
On Tue, Oct 22, 2013 at 7:44 AM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>
>> The EXYNOS5410 clocks are statically listed and registered
>> using the Samsung specific common clock helper functions.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>
> Looks good to me. Any objections for me to take this through the clk
> tree?
>
> Regards,
> Mike
>
>> ---
>> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
>> drivers/clk/samsung/Makefile | 1 +
>> drivers/clk/samsung/clk-exynos5410.c | 251 +++++++++++++++++++++
>> include/dt-bindings/clock/exynos5410.h | 175 ++++++++++++++
>> 4 files changed, 464 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>> create mode 100644 include/dt-bindings/clock/exynos5410.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> new file mode 100644
>> index 0000000..a462da231
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> @@ -0,0 +1,37 @@
>> +* Samsung Exynos5410 Clock Controller
>> +
>> +The Exynos5410 clock controller generates and supplies clock to various
>> +controllers within the Exynos5410 SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "samsung,exynos5410-clock"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/exynos5410.h header and can be used in device
>> +tree sources.
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> + clock: clock-controller at 0x10010000 {
>> + compatible = "samsung,exynos5410-clock";
>> + reg = <0x10010000 0x30000>;
>> + #clock-cells = <1>;
>> + };
>> +
>> +Example 2: UART controller node that consumes the clock generated by the clock
>> + controller. Refer to the standard clock bindings for information
>> + about 'clocks' and 'clock-names' property.
>> +
>> + serial at 12C20000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C00000 0x100>;
>> + interrupts = <0 51 0>;
>> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + };
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index 3413380..5a446ca 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -5,6 +5,7 @@
>> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
>> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
>> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
>> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
>> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
>> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
>> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
>> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
>> new file mode 100644
>> index 0000000..c5eba08
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos5410.c
>> @@ -0,0 +1,251 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Exynos5410 SoC.
>> +*/
>> +
>> +#include <dt-bindings/clock/exynos5410.h>
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +
>> +#include "clk.h"
>> +
>> +#define APLL_LOCK 0x0
>> +#define APLL_CON0 0x100
>> +#define CPLL_LOCK 0x10020
>> +#define CPLL_CON0 0x10120
>> +#define MPLL_LOCK 0x4000
>> +#define MPLL_CON0 0x4100
>> +#define BPLL_LOCK 0x20010
>> +#define BPLL_CON0 0x20110
>> +#define KPLL_LOCK 0x28000
>> +#define KPLL_CON0 0x28100
>> +
>> +#define SRC_CPU 0x200
>> +#define DIV_CPU0 0x500
>> +#define SRC_CPERI1 0x4204
>> +#define DIV_TOP0 0x10510
>> +#define DIV_TOP1 0x10514
>> +#define DIV_FSYS1 0x1054c
>> +#define DIV_FSYS2 0x10550
>> +#define DIV_PERIC0 0x10558
>> +#define SRC_TOP0 0x10210
>> +#define SRC_TOP1 0x10214
>> +#define SRC_TOP2 0x10218
>> +#define SRC_FSYS 0x10244
>> +#define SRC_PERIC0 0x10250
>> +#define SRC_MASK_FSYS 0x10340
>> +#define SRC_MASK_PERIC0 0x10350
>> +#define GATE_BUS_FSYS0 0x10740
>> +#define GATE_IP_FSYS 0x10944
>> +#define GATE_IP_PERIC 0x10950
>> +#define GATE_IP_PERIS 0x10960
>> +#define SRC_CDREX 0x20200
>> +#define SRC_KFC 0x28200
>> +#define DIV_KFC0 0x28500
>> +
>> +/* list of PLLs */
>> +enum exynos5410_plls {
>> + apll, cpll, mpll,
>> + bpll, kpll,
>> + nr_plls /* number of PLLs */
>> +};
>> +
>> +/*
>> + * list of controller registers to be saved and restored during a
>> + * suspend/resume cycle.
>> + */
>> +static unsigned long exynos5410_clk_regs[] __initdata = {
>> + SRC_CPU,
>> + DIV_CPU0,
>> + SRC_CPERI1,
>> + DIV_TOP0,
>> + DIV_TOP1,
>> + DIV_FSYS1,
>> + DIV_FSYS2,
>> + DIV_PERIC0,
>> + SRC_TOP0,
>> + SRC_TOP1,
>> + SRC_TOP2,
>> + SRC_FSYS,
>> + SRC_PERIC0,
>> + SRC_MASK_FSYS,
>> + SRC_MASK_PERIC0,
>> + GATE_BUS_FSYS0,
>> + GATE_IP_FSYS,
>> + GATE_IP_PERIC,
>> + GATE_IP_PERIS,
>> + SRC_CDREX,
>> + SRC_KFC,
>> + DIV_KFC0,
>> +};
>> +
>> +/* list of all parent clocks */
>> +PNAME(apll_p) = { "fin_pll", "fout_apll", };
>> +PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
>> +PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
>> +PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
>> +PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
>> +
>> +PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
>> +PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
>> +
>> +PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
>> +PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
>> +PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
>> +
>> +PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
>> + "none", "none", "sclk_mpll_bpll",
>> + "none", "none", "sclk_cpll" };
>> +
>> +/* fixed rate clocks generated outside the soc */
>> +static struct samsung_fixed_rate_clock exynos5410_frt_ext_clks[] __initdata = {
>> + FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
>> +};
>> +
>> +static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
>> + MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
>> + MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
>> +
>> + MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
>> + MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
>> +
>> + MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
>> + MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
>> +
>> + MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
>> + MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
>> +
>> + MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
>> +
>> + MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
>> +
>> + MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
>> + MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
>> + MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
>> +
>> + MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
>> + MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
>> + MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
>> +
>> + MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
>> + MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
>> +};
>> +
>> +static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
>> + DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
>> + DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
>> +
>> + DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
>> + DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
>> + DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
>> + DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
>> +
>> + DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
>> + DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
>> + DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
>> +
>> + DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
>> + DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
>> +
>> + DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>> + DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
>> + DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
>> +
>> + DIV_F(0, "div_mmc_pre0", "div_mmc0",
>> + DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
>> + DIV_F(0, "div_mmc_pre1", "div_mmc1",
>> + DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
>> + DIV_F(0, "div_mmc_pre2", "div_mmc2",
>> + DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
>> +
>> + DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
>> + DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
>> + DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
>> + DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
>> +
>> + DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
>> + DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
>> +};
>> +
>> +static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
>> + GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
>> +
>> + GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
>> + SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
>> + SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
>> + SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
>> +
>> + GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
>> + GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
>> + GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
>> +
>> + GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
>> + GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
>> + GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
>> +
>> + GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
>> + SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>> + SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>> + SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
>> +};
>> +
>> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
>> + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
>> + APLL_CON0, NULL),
>> + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
>> + CPLL_CON0, NULL),
>> + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
>> + MPLL_CON0, NULL),
>> + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
>> + BPLL_CON0, NULL),
>> + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
>> + KPLL_CON0, NULL),
>> +};
>> +
>> +static struct of_device_id ext_clk_match[] __initdata = {
>> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
>> + { },
>> +};
>> +
>> +/* register exynos5410 clocks */
>> +static void __init exynos5410_clk_init(struct device_node *np)
>> +{
>> + void __iomem *reg_base;
>> +
>> + reg_base = of_iomap(np, 0);
>> + if (!reg_base)
>> + panic("%s: failed to map registers\n", __func__);
>> +
>> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
>> + exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
>> + NULL, 0);
>> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
>> + ARRAY_SIZE(exynos5410_frt_ext_clks),
>> + ext_clk_match);
>> + samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
>> + reg_base);
>> +
>> + samsung_clk_register_mux(exynos5410_mux_clks,
>> + ARRAY_SIZE(exynos5410_mux_clks));
>> + samsung_clk_register_div(exynos5410_div_clks,
>> + ARRAY_SIZE(exynos5410_div_clks));
>> + samsung_clk_register_gate(exynos5410_gate_clks,
>> + ARRAY_SIZE(exynos5410_gate_clks));
>> +
>> + pr_debug("Exynos5410: clock setup completed.\n");
>> +}
>> +CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
>> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
>> new file mode 100644
>> index 0000000..9b4a58b
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/exynos5410.h
>> @@ -0,0 +1,175 @@
>> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
>> +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
>> +
>> +/* core clocks */
>> +#define CLK_FIN_PLL 1
>> +#define CLK_FOUT_APLL 2
>> +#define CLK_FOUT_CPLL 3
>> +#define CLK_FOUT_DPLL 4
>> +#define CLK_FOUT_EPLL 5
>> +#define CLK_FOUT_RPLL 6
>> +#define CLK_FOUT_IPLL 7
>> +#define CLK_FOUT_SPLL 8
>> +#define CLK_FOUT_VPLL 9
>> +#define CLK_FOUT_MPLL 10
>> +#define CLK_FOUT_BPLL 11
>> +#define CLK_FOUT_KPLL 12
>> +
>> +/* gate for special clocks (sclk) */
>> +#define CLK_SCLK_UART0 128
>> +#define CLK_SCLK_UART1 129
>> +#define CLK_SCLK_UART2 130
>> +#define CLK_SCLK_UART3 131
>> +#define CLK_SCLK_MMC0 132
>> +#define CLK_SCLK_MMC1 133
>> +#define CLK_SCLK_MMC2 134
>> +#define CLK_SCLK_SPI0 135
>> +#define CLK_SCLK_SPI1 136
>> +#define CLK_SCLK_SPI2 137
>> +#define CLK_SCLK_I2S1 138
>> +#define CLK_SCLK_I2S2 139
>> +#define CLK_SCLK_PCM1 140
>> +#define CLK_SCLK_PCM2 141
>> +#define CLK_SCLK_SPDIF 142
>> +#define CLK_SCLK_HDMI 143
>> +#define CLK_SCLK_PIXEL 144
>> +#define CLK_SCLK_DP1 145
>> +#define CLK_SCLK_MIPI1 146
>> +#define CLK_SCLK_FIMD1 147
>> +#define CLK_SCLK_MAUDIO0 148
>> +#define CLK_SCLK_MAUPCM0 149
>> +#define CLK_SCLK_USBD300 150
>> +#define CLK_SCLK_USBD301 151
>> +#define CLK_SCLK_USBPHY300 152
>> +#define CLK_SCLK_USBPHY301 153
>> +#define CLK_SCLK_UNIPRO 154
>> +#define CLK_SCLK_PWM 155
>> +#define CLK_SCLK_GSCL_WA 156
>> +#define CLK_SCLK_GSCL_WB 157
>> +#define CLK_SCLK_HDMIPHY 158
>> +
>> +/* gate clocks */
>> +#define CLK_ACLK66_PERIC 256
>> +#define CLK_UART0 257
>> +#define CLK_UART1 258
>> +#define CLK_UART2 259
>> +#define CLK_UART3 260
>> +#define CLK_I2C0 261
>> +#define CLK_I2C1 262
>> +#define CLK_I2C2 263
>> +#define CLK_I2C3 264
>> +#define CLK_I2C4 265
>> +#define CLK_I2C5 266
>> +#define CLK_I2C6 267
>> +#define CLK_I2C7 268
>> +#define CLK_I2C_HDMI 269
>> +#define CLK_TSADC 270
>> +#define CLK_SPI0 271
>> +#define CLK_SPI1 272
>> +#define CLK_SPI2 273
>> +#define CLK_KEYIF 274
>> +#define CLK_I2S1 275
>> +#define CLK_I2S2 276
>> +#define CLK_PCM1 277
>> +#define CLK_PCM2 278
>> +#define CLK_PWM 279
>> +#define CLK_SPDIF 280
>> +#define CLK_I2C8 281
>> +#define CLK_I2C9 282
>> +#define CLK_I2C10 283
>> +#define CLK_ACLK66_PSGEN 300
>> +#define CLK_CHIPID 301
>> +#define CLK_SYSREG 302
>> +#define CLK_TZPC0 303
>> +#define CLK_TZPC1 304
>> +#define CLK_TZPC2 305
>> +#define CLK_TZPC3 306
>> +#define CLK_TZPC4 307
>> +#define CLK_TZPC5 308
>> +#define CLK_TZPC6 309
>> +#define CLK_TZPC7 310
>> +#define CLK_TZPC8 311
>> +#define CLK_TZPC9 312
>> +#define CLK_HDMI_CEC 313
>> +#define CLK_SECKEY 314
>> +#define CLK_MCT 315
>> +#define CLK_WDT 316
>> +#define CLK_RTC 317
>> +#define CLK_TMU 318
>> +#define CLK_TMU_GPU 319
>> +#define CLK_PCLK66_GPIO 330
>> +#define CLK_ACLK200_FSYS2 350
>> +#define CLK_MMC0 351
>> +#define CLK_MMC1 352
>> +#define CLK_MMC2 353
>> +#define CLK_SROMC 354
>> +#define CLK_UFS 355
>> +#define CLK_ACLK200_FSYS 360
>> +#define CLK_TSI 361
>> +#define CLK_PDMA0 362
>> +#define CLK_PDMA1 363
>> +#define CLK_RTIC 364
>> +#define CLK_USBH20 365
>> +#define CLK_USBD300 366
>> +#define CLK_USBD301 367
>> +#define CLK_ACLK400_MSCL 380
>> +#define CLK_MSCL0 381
>> +#define CLK_MSCL1 382
>> +#define CLK_MSCL2 383
>> +#define CLK_SMMU_MSCL0 384
>> +#define CLK_SMMU_MSCL1 385
>> +#define CLK_SMMU_MSCL2 386
>> +#define CLK_ACLK333 400
>> +#define CLK_MFC 401
>> +#define CLK_SMMU_MFCL 402
>> +#define CLK_SMMU_MFCR 403
>> +#define CLK_ACLK200_DISP1 410
>> +#define CLK_DSIM1 411
>> +#define CLK_DP1 412
>> +#define CLK_HDMI 413
>> +#define CLK_ACLK300_DISP1 420
>> +#define CLK_FIMD1 421
>> +#define CLK_SMMU_FIMD1 422
>> +#define CLK_ACLK166 430
>> +#define CLK_MIXER 431
>> +#define CLK_ACLK266 440
>> +#define CLK_ROTATOR 441
>> +#define CLK_MDMA1 442
>> +#define CLK_SMMU_ROTATOR 443
>> +#define CLK_SMMU_MDMA1 444
>> +#define CLK_ACLK300_JPEG 450
>> +#define CLK_JPEG 451
>> +#define CLK_JPEG2 452
>> +#define CLK_SMMU_JPEG 453
>> +#define CLK_ACLK300_GSCL 460
>> +#define CLK_SMMU_GSCL0 461
>> +#define CLK_SMMU_GSCL1 462
>> +#define CLK_GSCL_WA 463
>> +#define CLK_GSCL_WB 464
>> +#define CLK_GSCL0 465
>> +#define CLK_GSCL1 466
>> +#define CLK_CLK_3AA 467
>> +#define CLK_ACLK266_G2D 470
>> +#define CLK_SSS 471
>> +#define CLK_SLIM_SSS 472
>> +#define CLK_MDMA0 473
>> +#define CLK_ACLK333_G2D 480
>> +#define CLK_G2D 481
>> +#define CLK_ACLK333_432_GSCL 490
>> +#define CLK_SMMU_3AA 491
>> +#define CLK_SMMU_FIMCL0 492
>> +#define CLK_SMMU_FIMCL1 493
>> +#define CLK_SMMU_FIMCL3 494
>> +#define CLK_FIMC_LITE3 495
>> +#define CLK_ACLK_G3D 500
>> +#define CLK_G3D 501
>> +#define CLK_SMMU_MIXER 502
>> +
>> +/* mux clocks */
>> +#define CLK_MOUT_HDMI 640
>> +
>> +/* divider clocks */
>> +#define CLK_DOUT_PIXEL 768
>> +#define CLK_NR_CLKS 769
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
>> --
>> 1.8.1.5
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-11-01 15:53 ` Mauro Ribeiro
@ 2013-11-01 16:25 ` Mauro Ribeiro
0 siblings, 0 replies; 25+ messages in thread
From: Mauro Ribeiro @ 2013-11-01 16:25 UTC (permalink / raw)
To: linux-arm-kernel
Nevermind, didn't read the clk-pll.c properly..
pll_35xx and pl_2550 will default to the same code.
Best Regards,
Mauro
On Fri, Nov 1, 2013 at 1:53 PM, Mauro Ribeiro <mdrjr0@gmail.com> wrote:
> Is the PLL35xx driver compatible with the ones used on 5410?
>
> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
> + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> + APLL_CON0, NULL),
> + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
> + CPLL_CON0, NULL),
> + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
> + MPLL_CON0, NULL),
> + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
> + BPLL_CON0, NULL),
> + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
> + KPLL_CON0, NULL),
>
> It registers all the PLL's with the same PLL. While the manual says
> others PLL names.
>
> Regards,
> Mauro
>
> On Tue, Oct 22, 2013 at 7:44 AM, Mike Turquette <mturquette@linaro.org> wrote:
>> Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
>>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>>
>>> The EXYNOS5410 clocks are statically listed and registered
>>> using the Samsung specific common clock helper functions.
>>>
>>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>>
>> Looks good to me. Any objections for me to take this through the clk
>> tree?
>>
>> Regards,
>> Mike
>>
>>> ---
>>> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
>>> drivers/clk/samsung/Makefile | 1 +
>>> drivers/clk/samsung/clk-exynos5410.c | 251 +++++++++++++++++++++
>>> include/dt-bindings/clock/exynos5410.h | 175 ++++++++++++++
>>> 4 files changed, 464 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>>> create mode 100644 include/dt-bindings/clock/exynos5410.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> new file mode 100644
>>> index 0000000..a462da231
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> @@ -0,0 +1,37 @@
>>> +* Samsung Exynos5410 Clock Controller
>>> +
>>> +The Exynos5410 clock controller generates and supplies clock to various
>>> +controllers within the Exynos5410 SoC.
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: should be "samsung,exynos5410-clock"
>>> +
>>> +- reg: physical base address of the controller and length of memory mapped
>>> + region.
>>> +
>>> +- #clock-cells: should be 1.
>>> +
>>> +All available clocks are defined as preprocessor macros in
>>> +dt-bindings/clock/exynos5410.h header and can be used in device
>>> +tree sources.
>>> +
>>> +Example 1: An example of a clock controller node is listed below.
>>> +
>>> + clock: clock-controller at 0x10010000 {
>>> + compatible = "samsung,exynos5410-clock";
>>> + reg = <0x10010000 0x30000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> +Example 2: UART controller node that consumes the clock generated by the clock
>>> + controller. Refer to the standard clock bindings for information
>>> + about 'clocks' and 'clock-names' property.
>>> +
>>> + serial at 12C20000 {
>>> + compatible = "samsung,exynos4210-uart";
>>> + reg = <0x12C00000 0x100>;
>>> + interrupts = <0 51 0>;
>>> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
>>> + clock-names = "uart", "clk_uart_baud0";
>>> + };
>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>> index 3413380..5a446ca 100644
>>> --- a/drivers/clk/samsung/Makefile
>>> +++ b/drivers/clk/samsung/Makefile
>>> @@ -5,6 +5,7 @@
>>> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
>>> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
>>> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
>>> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
>>> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
>>> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
>>> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
>>> diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
>>> new file mode 100644
>>> index 0000000..c5eba08
>>> --- /dev/null
>>> +++ b/drivers/clk/samsung/clk-exynos5410.c
>>> @@ -0,0 +1,251 @@
>>> +/*
>>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>>> + * Author: Tarek Dakhran <t.dakhran@samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * Common Clock Framework support for Exynos5410 SoC.
>>> +*/
>>> +
>>> +#include <dt-bindings/clock/exynos5410.h>
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/clkdev.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +
>>> +#include "clk.h"
>>> +
>>> +#define APLL_LOCK 0x0
>>> +#define APLL_CON0 0x100
>>> +#define CPLL_LOCK 0x10020
>>> +#define CPLL_CON0 0x10120
>>> +#define MPLL_LOCK 0x4000
>>> +#define MPLL_CON0 0x4100
>>> +#define BPLL_LOCK 0x20010
>>> +#define BPLL_CON0 0x20110
>>> +#define KPLL_LOCK 0x28000
>>> +#define KPLL_CON0 0x28100
>>> +
>>> +#define SRC_CPU 0x200
>>> +#define DIV_CPU0 0x500
>>> +#define SRC_CPERI1 0x4204
>>> +#define DIV_TOP0 0x10510
>>> +#define DIV_TOP1 0x10514
>>> +#define DIV_FSYS1 0x1054c
>>> +#define DIV_FSYS2 0x10550
>>> +#define DIV_PERIC0 0x10558
>>> +#define SRC_TOP0 0x10210
>>> +#define SRC_TOP1 0x10214
>>> +#define SRC_TOP2 0x10218
>>> +#define SRC_FSYS 0x10244
>>> +#define SRC_PERIC0 0x10250
>>> +#define SRC_MASK_FSYS 0x10340
>>> +#define SRC_MASK_PERIC0 0x10350
>>> +#define GATE_BUS_FSYS0 0x10740
>>> +#define GATE_IP_FSYS 0x10944
>>> +#define GATE_IP_PERIC 0x10950
>>> +#define GATE_IP_PERIS 0x10960
>>> +#define SRC_CDREX 0x20200
>>> +#define SRC_KFC 0x28200
>>> +#define DIV_KFC0 0x28500
>>> +
>>> +/* list of PLLs */
>>> +enum exynos5410_plls {
>>> + apll, cpll, mpll,
>>> + bpll, kpll,
>>> + nr_plls /* number of PLLs */
>>> +};
>>> +
>>> +/*
>>> + * list of controller registers to be saved and restored during a
>>> + * suspend/resume cycle.
>>> + */
>>> +static unsigned long exynos5410_clk_regs[] __initdata = {
>>> + SRC_CPU,
>>> + DIV_CPU0,
>>> + SRC_CPERI1,
>>> + DIV_TOP0,
>>> + DIV_TOP1,
>>> + DIV_FSYS1,
>>> + DIV_FSYS2,
>>> + DIV_PERIC0,
>>> + SRC_TOP0,
>>> + SRC_TOP1,
>>> + SRC_TOP2,
>>> + SRC_FSYS,
>>> + SRC_PERIC0,
>>> + SRC_MASK_FSYS,
>>> + SRC_MASK_PERIC0,
>>> + GATE_BUS_FSYS0,
>>> + GATE_IP_FSYS,
>>> + GATE_IP_PERIC,
>>> + GATE_IP_PERIS,
>>> + SRC_CDREX,
>>> + SRC_KFC,
>>> + DIV_KFC0,
>>> +};
>>> +
>>> +/* list of all parent clocks */
>>> +PNAME(apll_p) = { "fin_pll", "fout_apll", };
>>> +PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
>>> +PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
>>> +PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
>>> +PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
>>> +
>>> +PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
>>> +PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
>>> +
>>> +PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
>>> +PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
>>> +PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
>>> +
>>> +PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
>>> + "none", "none", "sclk_mpll_bpll",
>>> + "none", "none", "sclk_cpll" };
>>> +
>>> +/* fixed rate clocks generated outside the soc */
>>> +static struct samsung_fixed_rate_clock exynos5410_frt_ext_clks[] __initdata = {
>>> + FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
>>> +};
>>> +
>>> +static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
>>> + MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
>>> + MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
>>> +
>>> + MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
>>> + MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
>>> +
>>> + MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
>>> + MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
>>> +
>>> + MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
>>> + MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
>>> +
>>> + MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
>>> +
>>> + MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
>>> +
>>> + MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
>>> + MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
>>> + MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
>>> +
>>> + MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
>>> + MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
>>> + MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
>>> +
>>> + MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
>>> + MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
>>> +};
>>> +
>>> +static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
>>> + DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
>>> + DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
>>> +
>>> + DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
>>> + DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
>>> + DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
>>> + DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
>>> +
>>> + DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
>>> + DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
>>> + DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
>>> +
>>> + DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
>>> + DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
>>> +
>>> + DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>>> + DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
>>> + DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
>>> +
>>> + DIV_F(0, "div_mmc_pre0", "div_mmc0",
>>> + DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
>>> + DIV_F(0, "div_mmc_pre1", "div_mmc1",
>>> + DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
>>> + DIV_F(0, "div_mmc_pre2", "div_mmc2",
>>> + DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
>>> +
>>> + DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
>>> + DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
>>> + DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
>>> + DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
>>> +
>>> + DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
>>> + DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
>>> +};
>>> +
>>> +static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
>>> + GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
>>> +
>>> + GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
>>> + SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
>>> + GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
>>> + SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
>>> + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
>>> + SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
>>> +
>>> + GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
>>> + GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
>>> + GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
>>> +
>>> + GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
>>> + GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
>>> + GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
>>> +
>>> + GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
>>> + SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
>>> + GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
>>> + SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
>>> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
>>> + SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
>>> +};
>>> +
>>> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
>>> + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
>>> + APLL_CON0, NULL),
>>> + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
>>> + CPLL_CON0, NULL),
>>> + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
>>> + MPLL_CON0, NULL),
>>> + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
>>> + BPLL_CON0, NULL),
>>> + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
>>> + KPLL_CON0, NULL),
>>> +};
>>> +
>>> +static struct of_device_id ext_clk_match[] __initdata = {
>>> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
>>> + { },
>>> +};
>>> +
>>> +/* register exynos5410 clocks */
>>> +static void __init exynos5410_clk_init(struct device_node *np)
>>> +{
>>> + void __iomem *reg_base;
>>> +
>>> + reg_base = of_iomap(np, 0);
>>> + if (!reg_base)
>>> + panic("%s: failed to map registers\n", __func__);
>>> +
>>> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
>>> + exynos5410_clk_regs, ARRAY_SIZE(exynos5410_clk_regs),
>>> + NULL, 0);
>>> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
>>> + ARRAY_SIZE(exynos5410_frt_ext_clks),
>>> + ext_clk_match);
>>> + samsung_clk_register_pll(exynos5410_plls, ARRAY_SIZE(exynos5410_plls),
>>> + reg_base);
>>> +
>>> + samsung_clk_register_mux(exynos5410_mux_clks,
>>> + ARRAY_SIZE(exynos5410_mux_clks));
>>> + samsung_clk_register_div(exynos5410_div_clks,
>>> + ARRAY_SIZE(exynos5410_div_clks));
>>> + samsung_clk_register_gate(exynos5410_gate_clks,
>>> + ARRAY_SIZE(exynos5410_gate_clks));
>>> +
>>> + pr_debug("Exynos5410: clock setup completed.\n");
>>> +}
>>> +CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
>>> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
>>> new file mode 100644
>>> index 0000000..9b4a58b
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/exynos5410.h
>>> @@ -0,0 +1,175 @@
>>> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
>>> +#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
>>> +
>>> +/* core clocks */
>>> +#define CLK_FIN_PLL 1
>>> +#define CLK_FOUT_APLL 2
>>> +#define CLK_FOUT_CPLL 3
>>> +#define CLK_FOUT_DPLL 4
>>> +#define CLK_FOUT_EPLL 5
>>> +#define CLK_FOUT_RPLL 6
>>> +#define CLK_FOUT_IPLL 7
>>> +#define CLK_FOUT_SPLL 8
>>> +#define CLK_FOUT_VPLL 9
>>> +#define CLK_FOUT_MPLL 10
>>> +#define CLK_FOUT_BPLL 11
>>> +#define CLK_FOUT_KPLL 12
>>> +
>>> +/* gate for special clocks (sclk) */
>>> +#define CLK_SCLK_UART0 128
>>> +#define CLK_SCLK_UART1 129
>>> +#define CLK_SCLK_UART2 130
>>> +#define CLK_SCLK_UART3 131
>>> +#define CLK_SCLK_MMC0 132
>>> +#define CLK_SCLK_MMC1 133
>>> +#define CLK_SCLK_MMC2 134
>>> +#define CLK_SCLK_SPI0 135
>>> +#define CLK_SCLK_SPI1 136
>>> +#define CLK_SCLK_SPI2 137
>>> +#define CLK_SCLK_I2S1 138
>>> +#define CLK_SCLK_I2S2 139
>>> +#define CLK_SCLK_PCM1 140
>>> +#define CLK_SCLK_PCM2 141
>>> +#define CLK_SCLK_SPDIF 142
>>> +#define CLK_SCLK_HDMI 143
>>> +#define CLK_SCLK_PIXEL 144
>>> +#define CLK_SCLK_DP1 145
>>> +#define CLK_SCLK_MIPI1 146
>>> +#define CLK_SCLK_FIMD1 147
>>> +#define CLK_SCLK_MAUDIO0 148
>>> +#define CLK_SCLK_MAUPCM0 149
>>> +#define CLK_SCLK_USBD300 150
>>> +#define CLK_SCLK_USBD301 151
>>> +#define CLK_SCLK_USBPHY300 152
>>> +#define CLK_SCLK_USBPHY301 153
>>> +#define CLK_SCLK_UNIPRO 154
>>> +#define CLK_SCLK_PWM 155
>>> +#define CLK_SCLK_GSCL_WA 156
>>> +#define CLK_SCLK_GSCL_WB 157
>>> +#define CLK_SCLK_HDMIPHY 158
>>> +
>>> +/* gate clocks */
>>> +#define CLK_ACLK66_PERIC 256
>>> +#define CLK_UART0 257
>>> +#define CLK_UART1 258
>>> +#define CLK_UART2 259
>>> +#define CLK_UART3 260
>>> +#define CLK_I2C0 261
>>> +#define CLK_I2C1 262
>>> +#define CLK_I2C2 263
>>> +#define CLK_I2C3 264
>>> +#define CLK_I2C4 265
>>> +#define CLK_I2C5 266
>>> +#define CLK_I2C6 267
>>> +#define CLK_I2C7 268
>>> +#define CLK_I2C_HDMI 269
>>> +#define CLK_TSADC 270
>>> +#define CLK_SPI0 271
>>> +#define CLK_SPI1 272
>>> +#define CLK_SPI2 273
>>> +#define CLK_KEYIF 274
>>> +#define CLK_I2S1 275
>>> +#define CLK_I2S2 276
>>> +#define CLK_PCM1 277
>>> +#define CLK_PCM2 278
>>> +#define CLK_PWM 279
>>> +#define CLK_SPDIF 280
>>> +#define CLK_I2C8 281
>>> +#define CLK_I2C9 282
>>> +#define CLK_I2C10 283
>>> +#define CLK_ACLK66_PSGEN 300
>>> +#define CLK_CHIPID 301
>>> +#define CLK_SYSREG 302
>>> +#define CLK_TZPC0 303
>>> +#define CLK_TZPC1 304
>>> +#define CLK_TZPC2 305
>>> +#define CLK_TZPC3 306
>>> +#define CLK_TZPC4 307
>>> +#define CLK_TZPC5 308
>>> +#define CLK_TZPC6 309
>>> +#define CLK_TZPC7 310
>>> +#define CLK_TZPC8 311
>>> +#define CLK_TZPC9 312
>>> +#define CLK_HDMI_CEC 313
>>> +#define CLK_SECKEY 314
>>> +#define CLK_MCT 315
>>> +#define CLK_WDT 316
>>> +#define CLK_RTC 317
>>> +#define CLK_TMU 318
>>> +#define CLK_TMU_GPU 319
>>> +#define CLK_PCLK66_GPIO 330
>>> +#define CLK_ACLK200_FSYS2 350
>>> +#define CLK_MMC0 351
>>> +#define CLK_MMC1 352
>>> +#define CLK_MMC2 353
>>> +#define CLK_SROMC 354
>>> +#define CLK_UFS 355
>>> +#define CLK_ACLK200_FSYS 360
>>> +#define CLK_TSI 361
>>> +#define CLK_PDMA0 362
>>> +#define CLK_PDMA1 363
>>> +#define CLK_RTIC 364
>>> +#define CLK_USBH20 365
>>> +#define CLK_USBD300 366
>>> +#define CLK_USBD301 367
>>> +#define CLK_ACLK400_MSCL 380
>>> +#define CLK_MSCL0 381
>>> +#define CLK_MSCL1 382
>>> +#define CLK_MSCL2 383
>>> +#define CLK_SMMU_MSCL0 384
>>> +#define CLK_SMMU_MSCL1 385
>>> +#define CLK_SMMU_MSCL2 386
>>> +#define CLK_ACLK333 400
>>> +#define CLK_MFC 401
>>> +#define CLK_SMMU_MFCL 402
>>> +#define CLK_SMMU_MFCR 403
>>> +#define CLK_ACLK200_DISP1 410
>>> +#define CLK_DSIM1 411
>>> +#define CLK_DP1 412
>>> +#define CLK_HDMI 413
>>> +#define CLK_ACLK300_DISP1 420
>>> +#define CLK_FIMD1 421
>>> +#define CLK_SMMU_FIMD1 422
>>> +#define CLK_ACLK166 430
>>> +#define CLK_MIXER 431
>>> +#define CLK_ACLK266 440
>>> +#define CLK_ROTATOR 441
>>> +#define CLK_MDMA1 442
>>> +#define CLK_SMMU_ROTATOR 443
>>> +#define CLK_SMMU_MDMA1 444
>>> +#define CLK_ACLK300_JPEG 450
>>> +#define CLK_JPEG 451
>>> +#define CLK_JPEG2 452
>>> +#define CLK_SMMU_JPEG 453
>>> +#define CLK_ACLK300_GSCL 460
>>> +#define CLK_SMMU_GSCL0 461
>>> +#define CLK_SMMU_GSCL1 462
>>> +#define CLK_GSCL_WA 463
>>> +#define CLK_GSCL_WB 464
>>> +#define CLK_GSCL0 465
>>> +#define CLK_GSCL1 466
>>> +#define CLK_CLK_3AA 467
>>> +#define CLK_ACLK266_G2D 470
>>> +#define CLK_SSS 471
>>> +#define CLK_SLIM_SSS 472
>>> +#define CLK_MDMA0 473
>>> +#define CLK_ACLK333_G2D 480
>>> +#define CLK_G2D 481
>>> +#define CLK_ACLK333_432_GSCL 490
>>> +#define CLK_SMMU_3AA 491
>>> +#define CLK_SMMU_FIMCL0 492
>>> +#define CLK_SMMU_FIMCL1 493
>>> +#define CLK_SMMU_FIMCL3 494
>>> +#define CLK_FIMC_LITE3 495
>>> +#define CLK_ACLK_G3D 500
>>> +#define CLK_G3D 501
>>> +#define CLK_SMMU_MIXER 502
>>> +
>>> +/* mux clocks */
>>> +#define CLK_MOUT_HDMI 640
>>> +
>>> +/* divider clocks */
>>> +#define CLK_DOUT_PIXEL 768
>>> +#define CLK_NR_CLKS 769
>>> +
>>> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
>>> --
>>> 1.8.1.5
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-10-14 15:08 ` [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
2013-10-22 9:44 ` Mike Turquette
@ 2013-11-01 16:58 ` Tomasz Figa
2013-11-05 9:15 ` Tarek Dakhran
1 sibling, 1 reply; 25+ messages in thread
From: Tomasz Figa @ 2013-11-01 16:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 251
> +++++++++++++++++++++ include/dt-bindings/clock/exynos5410.h
> | 175 ++++++++++++++ 4 files changed, 464 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/exynos5410-clock.txt create
> mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
The driver looks pretty good now, thanks for addressing my comments to
previous version. There are still few issues remaining, though. Please see
my comments inline.
[snip]
> diff --git a/drivers/clk/samsung/clk-exynos5410.c
> b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644
> index 0000000..c5eba08
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
[snip]
> +static struct of_device_id ext_clk_match[] __initdata = {
> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
> + { },
> +};
I don't see anything in binding documentation mentioning this compatible
value. Anyway, since there is already a generic binding for fixed rate
clocks, this shouldn't be needed at all.
> +
> +/* register exynos5410 clocks */
> +static void __init exynos5410_clk_init(struct device_node *np)
> +{
> + void __iomem *reg_base;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base)
> + panic("%s: failed to map registers\n", __func__);
> +
> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
> + exynos5410_clk_regs,
ARRAY_SIZE(exynos5410_clk_regs),
> + NULL, 0);
> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
> + ARRAY_SIZE(exynos5410_frt_ext_clks),
> + ext_clk_match);
This call could be dropped after moving to generic fixed rate clock
bindings.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
@ 2013-11-01 17:08 ` Tomasz Figa
2013-11-01 21:52 ` Rob Herring
1 sibling, 0 replies; 25+ messages in thread
From: Tomasz Figa @ 2013-11-01 17:08 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 14 of October 2013 19:08:22 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 12 ++++++++++++
> arch/arm/mach-exynos/common.c | 18 ++++++++++++++++++
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
> 5 files changed, 40 insertions(+)
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
2013-10-14 15:08 ` [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410 Vyacheslav Tyrtov
@ 2013-11-01 17:09 ` Tomasz Figa
0 siblings, 0 replies; 25+ messages in thread
From: Tomasz Figa @ 2013-11-01 17:09 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 14 of October 2013 19:08:25 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
>
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++++++++++
> arch/arm/boot/dts/exynos5410.dtsi | 209
> ++++++++++++++++++++++++++++++ 3 files changed, 275 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
> create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
2013-11-01 17:08 ` Tomasz Figa
@ 2013-11-01 21:52 ` Rob Herring
2013-11-01 23:02 ` Tomasz Figa
1 sibling, 1 reply; 25+ messages in thread
From: Rob Herring @ 2013-11-01 21:52 UTC (permalink / raw)
To: linux-arm-kernel
On 10/14/2013 10:08 AM, Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran <t.dakhran@samsung.com>
>
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
I think this entire patch is mostly unnecessary and this information
should all be coming from DT. I'll leave it to arm-soc maintainers
whether they want to accept this addition rather than see some clean-up
here.
"samsung,exynos5410" does need to be documented though.
Rob
> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
> ---
> arch/arm/mach-exynos/Kconfig | 12 ++++++++++++
> arch/arm/mach-exynos/common.c | 18 ++++++++++++++++++
> arch/arm/mach-exynos/include/mach/map.h | 1 +
> arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
> arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
> 5 files changed, 40 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 56fe819..9ea1799 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -84,6 +84,18 @@ config SOC_EXYNOS5250
> help
> Enable EXYNOS5250 SoC support
>
> +config SOC_EXYNOS5410
> + bool "SAMSUNG EXYNOS5410"
> + default y
> + depends on ARCH_EXYNOS5
> + select MCPM
> + select ARM_CCI
> + select PM_GENERIC_DOMAINS if PM
> + select S5P_PM if PM
> + select S5P_SLEEP if PM
> + help
> + Enable EXYNOS5410 SoC support
> +
> config SOC_EXYNOS5420
> bool "SAMSUNG EXYNOS5420"
> default y
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index ba95e5d..187c0a4 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
> static const char name_exynos4212[] = "EXYNOS4212";
> static const char name_exynos4412[] = "EXYNOS4412";
> static const char name_exynos5250[] = "EXYNOS5250";
> +static const char name_exynos5410[] = "EXYNOS5410";
> static const char name_exynos5420[] = "EXYNOS5420";
> static const char name_exynos5440[] = "EXYNOS5440";
>
> @@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
> .init = exynos_init,
> .name = name_exynos5250,
> }, {
> + .idcode = EXYNOS5410_SOC_ID,
> + .idmask = EXYNOS5_SOC_MASK,
> + .map_io = exynos5_map_io,
> + .init = exynos_init,
> + .name = name_exynos5410,
> + }, {
> .idcode = EXYNOS5420_SOC_ID,
> .idmask = EXYNOS5_SOC_MASK,
> .map_io = exynos5_map_io,
> @@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
> },
> };
>
> +static struct map_desc exynos5410_iodesc[] __initdata = {
> + {
> + .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
> + .pfn = __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
> + .length = SZ_4K,
> + .type = MT_DEVICE,
> + },
> +};
> +
> static struct map_desc exynos5250_iodesc[] __initdata = {
> {
> .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
> @@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
>
> if (soc_is_exynos5250())
> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
> + if (soc_is_exynos5410())
> + iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
> }
>
> void __init exynos_init_time(void)
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 7b046b5..894f431 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -29,6 +29,7 @@
> #define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
> #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
> #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
> +#define EXYNOS5410_PA_SYSRAM_NS 0x02073000
>
> #define EXYNOS_PA_CHIPID 0x10000000
>
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index f874b77..9515186 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
>
> static char const *exynos5_dt_compat[] __initdata = {
> "samsung,exynos5250",
> + "samsung,exynos5410",
> "samsung,exynos5420",
> "samsung,exynos5440",
> NULL
> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
> index 4fb1f03..aad7c40 100644
> --- a/arch/arm/plat-samsung/include/plat/cpu.h
> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
> @@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
> #define EXYNOS4_CPU_MASK 0xFFFE0000
>
> #define EXYNOS5250_SOC_ID 0x43520000
> +#define EXYNOS5410_SOC_ID 0xE5410023
> #define EXYNOS5420_SOC_ID 0xE5420000
> #define EXYNOS5440_SOC_ID 0xE5440000
> #define EXYNOS5_SOC_MASK 0xFFFFF000
> @@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
> +IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
> IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
> IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>
> @@ -144,6 +146,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
> # define soc_is_exynos5250() 0
> #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5410)
> +# define soc_is_exynos5410() is_samsung_exynos5410()
> +#else
> +# define soc_is_exynos5410() 0
> +#endif
> +
> #if defined(CONFIG_SOC_EXYNOS5420)
> # define soc_is_exynos5420() is_samsung_exynos5420()
> #else
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
2013-11-01 21:52 ` Rob Herring
@ 2013-11-01 23:02 ` Tomasz Figa
0 siblings, 0 replies; 25+ messages in thread
From: Tomasz Figa @ 2013-11-01 23:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
On Friday 01 of November 2013 16:52:44 Rob Herring wrote:
> On 10/14/2013 10:08 AM, Vyacheslav Tyrtov wrote:
> > From: Tarek Dakhran <t.dakhran@samsung.com>
> >
> > EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> > Add initial support for this SoC.
>
> I think this entire patch is mostly unnecessary and this information
> should all be coming from DT. I'll leave it to arm-soc maintainers
> whether they want to accept this addition rather than see some clean-up
> here.
The clean-up here is already in plans, but this is much more than can be
seen just from this patch, so it needs some time.
>
> "samsung,exynos5410" does need to be documented though.
Right.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
2013-10-25 10:06 ` Aliaksei Katovich
@ 2013-11-04 10:42 ` Alexei Colin
2013-11-04 17:12 ` Alexei Colin
0 siblings, 1 reply; 25+ messages in thread
From: Alexei Colin @ 2013-11-04 10:42 UTC (permalink / raw)
To: linux-arm-kernel
Aliaksei,
On 12/31/1969 07:00 PM, wrote:
>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>
>> Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
>> This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>> arch/arm/mach-exynos/Makefile | 2 +
>> arch/arm/mach-exynos/edcs.c | 270 ++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 272 insertions(+)
>> create mode 100644 arch/arm/mach-exynos/edcs.c
>>
[snip]
>> +
>> +/*
>> + * Enable cluster-level coherency, in preparation for turning on the MMU.
>> + */
>> +static void __naked edcs_power_up_setup(unsigned int affinity_level)
>> +{
>> + asm volatile ("\n"
>> + "b cci_enable_port_for_self");
>> +}
>
> This code breaks odroid-xu boot with NR_CPUS set to 8. Kernel panics
> like this:
>
> %< -----------------------------------------------------------------------
> [ 5.315000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
> [ 5.320000] Freeing unused kernel memory: 216K (c049b000 - c04d1000)
> [ 5.325000] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
> [ 5.340000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
> [ 5.340000]
> [ 5.345000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 200000Hz, actual 200000HZ div = 250)
> [ 5.355000] CPU: 3 PID: 1 Comm: init Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
> [ 5.365000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
> [ 5.370000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
> [ 5.380000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 196079Hz, actual 196078HZ div = 255)
> [ 5.390000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c03609fc>] (panic+0x90/0x1e8)
> [ 5.395000] [<c03609fc>] (panic+0x90/0x1e8) from [<c002048c>] (do_exit+0x780/0x834)
> [ 5.405000] [<c002048c>] (do_exit+0x780/0x834) from [<c002062c>] (do_group_exit+0x3c/0xb0)
> [ 5.410000] [<c002062c>] (do_group_exit+0x3c/0xb0) from [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534)
> [ 5.420000] [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534) from [<c0010d08>] (do_signal+0x100/0x40c)
> [ 5.430000] [<c0010d08>] (do_signal+0x100/0x40c) from [<c0011348>] (do_work_pending+0x68/0xa8)
> [ 5.430000] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 50000000Hz, actual 50000000HZ div = 1)
> [ 5.430000] mmc1: new high speed SDHC card at address b368
> [ 5.435000] mmcblk0: mmc1:b368 USD 14.9 GiB
> [ 5.440000] mmcblk0: p1 p2 p3 < p5 p6 p7 >
> [ 5.455000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz, actual 400000HZ div = 125)
> [ 5.475000] [<c0011348>] (do_work_pending+0x68/0xa8) from [<c000e420>] (work_pending+0xc/0x20)
> [ 5.480000] CPU1: stopping
> [ 5.480000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
> [ 5.480000] Exception stack(0xef0a7f88 to 0xef0a7fd0)
> [ 5.480000] 7f80: 00000001 00000000 008d20ff 00000001 00000000 00000000
> [ 5.480000] 7fa0: c04d07a0 60000113 010da000 412fc0f3 c15aa7a0 00000000 00000001 ef0a7fd0
> [ 5.480000] 7fc0: c0072d74 c0072d78 20000113 ffffffff
> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c0072d78>] (rcu_idle_exit+0x68/0xb8)
> [ 5.480000] [<c0072d78>] (rcu_idle_exit+0x68/0xb8) from [<c00550a4>] (cpu_startup_entry+0x6c/0x148)
> [ 5.480000] [<c00550a4>] (cpu_startup_entry+0x6c/0x148) from [<400085c4>] (0x400085c4)
> [ 5.480000] CPU0: stopping
> [ 5.480000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
> [ 5.480000] Exception stack(0xc04d3f70 to 0xc04d3fb8)
> [ 5.480000] SMP: failed to stop secondary CPUs
> [ 5.480000] 3f60: 00000000 00000000 00002190 00000000
> [ 5.480000] 3f80: c04d2000 c050a88f 00000001 c050a88f c04da44c 412fc0f3 c036a960 00000000
> [ 5.480000] 3fa0: 00000020 c04d3fb8 c000f5d4 c000f5d8 60000113 ffffffff
> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
> [ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
> [ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<c049ba9c>] (start_kernel+0x32c/0x384)
> [ 5.480000] CPU2: stopping
> [ 5.480000] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
> [ 5.480000] Exception stack(0xef0a9fa0 to 0xef0a9fe8)
> [ 5.480000] 9fa0: 00000002 00000000 008e4858 00000000 ef0a8000 c050a88f 00000001 c050a88f
> [ 5.480000] 9fc0: c04da44c 412fc0f3 c036a960 00000000 00000001 ef0a9fe8 c000f5d4 c000f5d8
> [ 5.480000] 9fe0: 60000113 ffffffff
> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
> [ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
> [ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<400085c4>] (0x400085c4)
> %< -----------------------------------------------------------------------
>
> I checked arch/arm/mach-vexpress/tc2_pm.c to see how CCI is enabled
> there an realized that you should follow same pattern, i.e.:
>
> asm volatile (" \n"
> " cmp r0, #1 \n"
> " bxne lr \n"
> " b cci_enable_port_for_self ");
>
> In this case only one cluster (4 LITTLE cores for Exynos5410) will be
> initialized at boot time. And no panic.
After this modification the same crash goes away for me too: Odroid
XU+E, 3.12-rc5 + this patchset, exynos_defconfig, exynos5410-smdk5410.dtb.
But, the other four cores fail to come online at boot time and fail when
manually brought online 'echo 1 > /sys/devices/system/cpu/cpu4/online'.
The write of S5P_CORE_LOCAL_PWR_EN to EDCS_CORE_CONFIGURATION happens
but the CPU never reaches mcpm_entry_point.
If I change the above to 'cmp r0, #0' (the A15 cluster?), then I get the
same crash as with unconditional call, and _the same_ 4 CPUs online.
Does this mean that enabling coherence for the A15 cluster causes the
above crash? And, is it true that for the A15 CPUs to wake up and
proceed to the entry point coherence must be enabled (or is some other
reason preventing them from waking up)?
[ 0.045000] CPU: Testing write buffer coherency: ok
[ 0.050000] CPU0: update cpu_power 1468
[ 0.055000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.060000] Setting up static identity map for 0xc038c4b8 - 0xc038c510
[ 0.065000] ARM CCI driver probed
[ 0.065000] edcs_init: configuring entry points
[ 0.070000] edcs_init: calling data init
[ 0.075000] edcs_data_init: cpu 0 cluster 0
[ 0.080000] EDCS power management initialized
[ 0.115000] exynos_power_up: cpu 1 cluster 0
[ 0.115000] exynos_power_up: cpu 1 cluster 0 use count 1
[ 0.115000] exynos_core_power_control: changing value to 3
CPU01 cluster00: kernel mcpm_entry_point
CPU01 cluster00: released
[ 0.125000] CPU1: Booted secondary processor
[ 0.125000] mcpm_cpu_powered_up: up
[ 0.160000] CPU1: update cpu_power 1468
[ 0.165000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.175000] exynos_power_up: cpu 2 cluster 0
[ 0.180000] exynos_power_up: cpu 2 cluster 0 use count 1
[ 0.180000] exynos_core_power_control: changing value to 3
CPU02 cluster00: kernel mcpm_entry_point
CPU02 cluster00: released
[ 0.190000] CPU2: Booted secondary processor
...
[ 0.280000] exynos_power_up: cpu 0 cluster 1
[ 0.285000] exynos_power_up: cpu 0 cluster 1 use count 1
[ 0.285000] exynos_core_power_control: changing value to 3
[ 1.290000] CPU4: failed to come online
[ 1.300000] exynos_power_up: cpu 1 cluster 1
[ 1.300000] exynos_power_up: cpu 1 cluster 1 use count 1
[ 1.300000] exynos_core_power_control: changing value to 3
[ 2.305000] CPU5: failed to come online
...
[ 4.340000] SMP: Total of 4 processors activated.
[ 4.345000] CPU: All CPU(s) started in SVC mode.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
2013-11-04 10:42 ` Alexei Colin
@ 2013-11-04 17:12 ` Alexei Colin
0 siblings, 0 replies; 25+ messages in thread
From: Alexei Colin @ 2013-11-04 17:12 UTC (permalink / raw)
To: linux-arm-kernel
On 11/04/2013 05:42 AM, Alexei Colin wrote:
> Aliaksei,
>
> On 12/31/1969 07:00 PM, wrote:
>>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>>
>>> Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
>>> This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
>>>
>>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>>> ---
>>> arch/arm/mach-exynos/Makefile | 2 +
>>> arch/arm/mach-exynos/edcs.c | 270 ++++++++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 272 insertions(+)
>>> create mode 100644 arch/arm/mach-exynos/edcs.c
>>>
> [snip]
>>> +
>>> +/*
>>> + * Enable cluster-level coherency, in preparation for turning on the MMU.
>>> + */
>>> +static void __naked edcs_power_up_setup(unsigned int affinity_level)
>>> +{
>>> + asm volatile ("\n"
>>> + "b cci_enable_port_for_self");
>>> +}
>>
>> This code breaks odroid-xu boot with NR_CPUS set to 8. Kernel panics
>> like this:
>>
>> %< -----------------------------------------------------------------------
>> [ 5.315000] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
>> [ 5.320000] Freeing unused kernel memory: 216K (c049b000 - c04d1000)
>> [ 5.325000] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
>> [ 5.340000] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
>> [ 5.340000]
>> [ 5.345000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 200000Hz, actual 200000HZ div = 250)
>> [ 5.355000] CPU: 3 PID: 1 Comm: init Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
>> [ 5.365000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
>> [ 5.370000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
>> [ 5.380000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 196079Hz, actual 196078HZ div = 255)
>> [ 5.390000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c03609fc>] (panic+0x90/0x1e8)
>> [ 5.395000] [<c03609fc>] (panic+0x90/0x1e8) from [<c002048c>] (do_exit+0x780/0x834)
>> [ 5.405000] [<c002048c>] (do_exit+0x780/0x834) from [<c002062c>] (do_group_exit+0x3c/0xb0)
>> [ 5.410000] [<c002062c>] (do_group_exit+0x3c/0xb0) from [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534)
>> [ 5.420000] [<c002ae80>] (get_signal_to_deliver+0x1d4/0x534) from [<c0010d08>] (do_signal+0x100/0x40c)
>> [ 5.430000] [<c0010d08>] (do_signal+0x100/0x40c) from [<c0011348>] (do_work_pending+0x68/0xa8)
>> [ 5.430000] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 50000000Hz, actual 50000000HZ div = 1)
>> [ 5.430000] mmc1: new high speed SDHC card at address b368
>> [ 5.435000] mmcblk0: mmc1:b368 USD 14.9 GiB
>> [ 5.440000] mmcblk0: p1 p2 p3 < p5 p6 p7 >
>> [ 5.455000] mmc_host mmc0: Bus speed (slot 0) = 100000000Hz (slot req 400000Hz, actual 400000HZ div = 125)
>> [ 5.475000] [<c0011348>] (do_work_pending+0x68/0xa8) from [<c000e420>] (work_pending+0xc/0x20)
>> [ 5.480000] CPU1: stopping
>> [ 5.480000] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
>> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
>> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
>> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
>> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
>> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
>> [ 5.480000] Exception stack(0xef0a7f88 to 0xef0a7fd0)
>> [ 5.480000] 7f80: 00000001 00000000 008d20ff 00000001 00000000 00000000
>> [ 5.480000] 7fa0: c04d07a0 60000113 010da000 412fc0f3 c15aa7a0 00000000 00000001 ef0a7fd0
>> [ 5.480000] 7fc0: c0072d74 c0072d78 20000113 ffffffff
>> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c0072d78>] (rcu_idle_exit+0x68/0xb8)
>> [ 5.480000] [<c0072d78>] (rcu_idle_exit+0x68/0xb8) from [<c00550a4>] (cpu_startup_entry+0x6c/0x148)
>> [ 5.480000] [<c00550a4>] (cpu_startup_entry+0x6c/0x148) from [<400085c4>] (0x400085c4)
>> [ 5.480000] CPU0: stopping
>> [ 5.480000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
>> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
>> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
>> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
>> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
>> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
>> [ 5.480000] Exception stack(0xc04d3f70 to 0xc04d3fb8)
>> [ 5.480000] SMP: failed to stop secondary CPUs
>> [ 5.480000] 3f60: 00000000 00000000 00002190 00000000
>> [ 5.480000] 3f80: c04d2000 c050a88f 00000001 c050a88f c04da44c 412fc0f3 c036a960 00000000
>> [ 5.480000] 3fa0: 00000020 c04d3fb8 c000f5d4 c000f5d8 60000113 ffffffff
>> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
>> [ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
>> [ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<c049ba9c>] (start_kernel+0x32c/0x384)
>> [ 5.480000] CPU2: stopping
>> [ 5.480000] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 3.12.0-rc5-00006-g847e427-dirty #1
>> [ 5.480000] [<c0014d40>] (unwind_backtrace+0x0/0xf8) from [<c00117cc>] (show_stack+0x10/0x14)
>> [ 5.480000] [<c00117cc>] (show_stack+0x10/0x14) from [<c03633ac>] (dump_stack+0x6c/0xac)
>> [ 5.480000] [<c03633ac>] (dump_stack+0x6c/0xac) from [<c0013604>] (handle_IPI+0xf8/0x11c)
>> [ 5.480000] [<c0013604>] (handle_IPI+0xf8/0x11c) from [<c000851c>] (gic_handle_irq+0x60/0x68)
>> [ 5.480000] [<c000851c>] (gic_handle_irq+0x60/0x68) from [<c00122c0>] (__irq_svc+0x40/0x70)
>> [ 5.480000] Exception stack(0xef0a9fa0 to 0xef0a9fe8)
>> [ 5.480000] 9fa0: 00000002 00000000 008e4858 00000000 ef0a8000 c050a88f 00000001 c050a88f
>> [ 5.480000] 9fc0: c04da44c 412fc0f3 c036a960 00000000 00000001 ef0a9fe8 c000f5d4 c000f5d8
>> [ 5.480000] 9fe0: 60000113 ffffffff
>> [ 5.480000] [<c00122c0>] (__irq_svc+0x40/0x70) from [<c000f5d8>] (arch_cpu_idle+0x28/0x30)
>> [ 5.480000] [<c000f5d8>] (arch_cpu_idle+0x28/0x30) from [<c0055094>] (cpu_startup_entry+0x5c/0x148)
>> [ 5.480000] [<c0055094>] (cpu_startup_entry+0x5c/0x148) from [<400085c4>] (0x400085c4)
>> %< -----------------------------------------------------------------------
>>
>> I checked arch/arm/mach-vexpress/tc2_pm.c to see how CCI is enabled
>> there an realized that you should follow same pattern, i.e.:
>>
>> asm volatile (" \n"
>> " cmp r0, #1 \n"
>> " bxne lr \n"
>> " b cci_enable_port_for_self ");
>>
>> In this case only one cluster (4 LITTLE cores for Exynos5410) will be
>> initialized at boot time. And no panic.
>
> After this modification the same crash goes away for me too: Odroid
> XU+E, 3.12-rc5 + this patchset, exynos_defconfig, exynos5410-smdk5410.dtb.
>
> But, the other four cores fail to come online at boot time and fail when
> manually brought online 'echo 1 > /sys/devices/system/cpu/cpu4/online'.
> The write of S5P_CORE_LOCAL_PWR_EN to EDCS_CORE_CONFIGURATION happens
> but the CPU never reaches mcpm_entry_point.
>
> If I change the above to 'cmp r0, #0' (the A15 cluster?), then I get the
> same crash as with unconditional call, and _the same_ 4 CPUs online.
> Does this mean that enabling coherence for the A15 cluster causes the
> above crash? And, is it true that for the A15 CPUs to wake up and
> proceed to the entry point coherence must be enabled (or is some other
> reason preventing them from waking up)?
Just realized that the argument to power_up_setup is not the cluster but
"affinity," which is 1 for clusters and 0 for cores (?). This explains
Aliaksei's correction and renders my above experiment pointless.
This code that enables coherency happens much later than
mcpm_entry_point. So, this strengthens the hypothesis that CPUs from the
other cluster don't come online due to some other reason. Is there an
explit "turn on cluster" operation that needs to happen before (or
after) the register write in exynos_core_power_control can turn on a
core in that cluster?
>
> [ 0.045000] CPU: Testing write buffer coherency: ok
> [ 0.050000] CPU0: update cpu_power 1468
> [ 0.055000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.060000] Setting up static identity map for 0xc038c4b8 - 0xc038c510
> [ 0.065000] ARM CCI driver probed
> [ 0.065000] edcs_init: configuring entry points
> [ 0.070000] edcs_init: calling data init
> [ 0.075000] edcs_data_init: cpu 0 cluster 0
> [ 0.080000] EDCS power management initialized
> [ 0.115000] exynos_power_up: cpu 1 cluster 0
> [ 0.115000] exynos_power_up: cpu 1 cluster 0 use count 1
> [ 0.115000] exynos_core_power_control: changing value to 3
> CPU01 cluster00: kernel mcpm_entry_point
> CPU01 cluster00: released
> [ 0.125000] CPU1: Booted secondary processor
> [ 0.125000] mcpm_cpu_powered_up: up
> [ 0.160000] CPU1: update cpu_power 1468
> [ 0.165000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 0.175000] exynos_power_up: cpu 2 cluster 0
> [ 0.180000] exynos_power_up: cpu 2 cluster 0 use count 1
> [ 0.180000] exynos_core_power_control: changing value to 3
> CPU02 cluster00: kernel mcpm_entry_point
> CPU02 cluster00: released
> [ 0.190000] CPU2: Booted secondary processor
> ...
> [ 0.280000] exynos_power_up: cpu 0 cluster 1
> [ 0.285000] exynos_power_up: cpu 0 cluster 1 use count 1
> [ 0.285000] exynos_core_power_control: changing value to 3
> [ 1.290000] CPU4: failed to come online
> [ 1.300000] exynos_power_up: cpu 1 cluster 1
> [ 1.300000] exynos_power_up: cpu 1 cluster 1 use count 1
> [ 1.300000] exynos_core_power_control: changing value to 3
> [ 2.305000] CPU5: failed to come online
> ...
> [ 4.340000] SMP: Total of 4 processors activated.
> [ 4.345000] CPU: All CPU(s) started in SVC mode.
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
2013-11-01 16:58 ` Tomasz Figa
@ 2013-11-05 9:15 ` Tarek Dakhran
0 siblings, 0 replies; 25+ messages in thread
From: Tarek Dakhran @ 2013-11-05 9:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 01.11.2013 20:58, Tomasz Figa wrote:
> Hi,
>
> On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
>> From: Tarek Dakhran <t.dakhran@samsung.com>
>>
>> The EXYNOS5410 clocks are statically listed and registered
>> using the Samsung specific common clock helper functions.
>>
>> Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
>> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
>> ---
>> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
>> drivers/clk/samsung/Makefile | 1 +
>> drivers/clk/samsung/clk-exynos5410.c | 251
>> +++++++++++++++++++++ include/dt-bindings/clock/exynos5410.h
>> | 175 ++++++++++++++ 4 files changed, 464 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos5410-clock.txt create
>> mode 100644 drivers/clk/samsung/clk-exynos5410.c
>> create mode 100644 include/dt-bindings/clock/exynos5410.h
> The driver looks pretty good now, thanks for addressing my comments to
> previous version. There are still few issues remaining, though. Please see
> my comments inline.
>
> [snip]
>> diff --git a/drivers/clk/samsung/clk-exynos5410.c
>> b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644
>> index 0000000..c5eba08
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos5410.c
> [snip]
>> +static struct of_device_id ext_clk_match[] __initdata = {
>> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
>> + { },
>> +};
> I don't see anything in binding documentation mentioning this compatible
> value. Anyway, since there is already a generic binding for fixed rate
> clocks, this shouldn't be needed at all.
>
>> +
>> +/* register exynos5410 clocks */
>> +static void __init exynos5410_clk_init(struct device_node *np)
>> +{
>> + void __iomem *reg_base;
>> +
>> + reg_base = of_iomap(np, 0);
>> + if (!reg_base)
>> + panic("%s: failed to map registers\n", __func__);
>> +
>> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
>> + exynos5410_clk_regs,
> ARRAY_SIZE(exynos5410_clk_regs),
>> + NULL, 0);
>> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
>> + ARRAY_SIZE(exynos5410_frt_ext_clks),
>> + ext_clk_match);
> This call could be dropped after moving to generic fixed rate clock
> bindings.
>
> Best regards,
> Tomasz
Already done. Will be added in patch v3.
Thank you for comments, Tomasz.
Best regards,
Tarek Dakhran
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2013-11-05 9:15 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-10-14 15:08 [PATCH v2 0/4] Exynos 5410 Dual cluster support Vyacheslav Tyrtov
2013-10-14 15:08 ` [PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC Vyacheslav Tyrtov
2013-11-01 17:08 ` Tomasz Figa
2013-11-01 21:52 ` Rob Herring
2013-11-01 23:02 ` Tomasz Figa
2013-10-14 15:08 ` [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework Vyacheslav Tyrtov
2013-10-22 9:44 ` Mike Turquette
2013-11-01 15:53 ` Mauro Ribeiro
2013-11-01 16:25 ` Mauro Ribeiro
2013-11-01 16:58 ` Tomasz Figa
2013-11-05 9:15 ` Tarek Dakhran
2013-10-14 15:08 ` [PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support Vyacheslav Tyrtov
2013-10-17 10:45 ` Daniel Lezcano
2013-10-25 10:06 ` Aliaksei Katovich
2013-11-04 10:42 ` Alexei Colin
2013-11-04 17:12 ` Alexei Colin
2013-10-14 15:08 ` [PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410 Vyacheslav Tyrtov
2013-11-01 17:09 ` Tomasz Figa
2013-10-16 22:15 ` [PATCH v2 0/4] Exynos 5410 Dual cluster support Kevin Hilman
2013-10-17 13:04 ` Aliaksei Katovich
2013-10-17 13:51 ` Tarek Dakhran
2013-10-17 14:24 ` Aliaksei Katovich
2013-10-17 14:02 ` Tarek Dakhran
2013-10-17 20:00 ` Kevin Hilman
[not found] ` <CAGc3s_cbCgdPdbCPF2XN+p-O5RfM-4pNZT49=_4MOVy=Lz8d=Q@mail.gmail.com>
2013-10-30 23:57 ` Kevin Hilman
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