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From: Marc Zyngier <maz@kernel.org>
To: Peter Collingbourne <pcc@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Yichao Yu <yyc1992@gmail.com>,
	"Robert O'Callahan" <robert@ocallahan.org>,
	Keno Fischer <keno@juliacomputing.com>
Subject: Re: [PATCH] arm64: Implement prctl(PR_{G,S}ET_TSC)
Date: Sun, 28 Apr 2024 11:37:34 +0100	[thread overview]
Message-ID: <87h6flu61d.wl-maz@kernel.org> (raw)
In-Reply-To: <20240427052754.2014024-1-pcc@google.com>

On Sat, 27 Apr 2024 06:27:51 +0100,
Peter Collingbourne <pcc@google.com> wrote:
> 
> On arm64, this prctl controls access to CNTVCT_EL0, CNTVCTSS_EL0 and
> CNTFRQ_EL0 via CNTKCTL_EL1.EL0VCTEN. Since this bit is also used to
> implement various erratum workarounds, check whether the CPU needs
> a workaround whenever we potentially need to change it.

Why would we ever consider preventing access to CNTVTL_EL0?  This
register is part of the arm64 ABI, together with CNTFRQ_EL0.
Disabling it also prevents the VDSO from working correctly, making
something as simple as getttimeofday() unexpectedly fail.

I'm sure you have some rationale behind it, but it is nowhere to be
found above, and I cannot see why we'd want to mimic whatever x86
does.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2024-04-28 10:38 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-27  5:27 [PATCH] arm64: Implement prctl(PR_{G,S}ET_TSC) Peter Collingbourne
2024-04-28 10:37 ` Marc Zyngier [this message]
2024-04-28 18:47   ` Peter Collingbourne
2024-04-29  7:34     ` Marc Zyngier
2024-04-29  8:35       ` Keno Fischer
2024-04-29 18:46         ` Peter Collingbourne

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