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Thu, 01 Apr 2021 17:03:17 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lS0iu-00AR9y-Vs for linux-arm-kernel@lists.infradead.org; Thu, 01 Apr 2021 17:03:14 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6A76F61220; Thu, 1 Apr 2021 17:03:11 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lS0ir-005850-D6; Thu, 01 Apr 2021 18:03:09 +0100 Date: Thu, 01 Apr 2021 18:03:09 +0100 Message-ID: <87h7kqey42.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: Disable fine grained traps on boot In-Reply-To: <20210401154805.GL4758@sirena.org.uk> References: <20210401124936.56877-1-broonie@kernel.org> <87sg4aox44.wl-maz@kernel.org> <20210401154805.GL4758@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_180313_193306_416C4F4B X-CRM114-Status: GOOD ( 24.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 01 Apr 2021 16:48:05 +0100, Mark Brown wrote: > > On Thu, Apr 01, 2021 at 04:14:35PM +0100, Marc Zyngier wrote: > > On Thu, 01 Apr 2021 13:49:36 +0100, > > Mark Brown wrote: > > > > + msr_s SYS_HFGRTR_EL2, xzr > > > + msr_s SYS_HFGITR_EL2, xzr > > > + msr_s SYS_HFGWTR_EL2, xzr > > > nit: consider grouping SYS_HFGWTR_EL2 and SYS_HFGRTR_EL2 together, > > since they affect the same registers. > > Ack, I'd sorted them numerically IIRC. > > > > + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU > > > + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4 > > > + cbz x1, .Lskip_fgt_\@ > > > > + msr_s SYS_HAFGRTR_EL2, xzr > > > Do we need to document the need for SCR_EL3.FGTEn to be set so that > > these register accesses don't trap? That'd be consistent with what we > > do for other features (PtrAuth, AMU...). > > Yes, good point. We should if this is going in - this is the result of > some other stuff I've been sending to document disabling these on boot, > Will wanted to have code doing that, so I'll pull that into there. It > does end up being a bit weird that we demand this be enabled so we can > explicitly not use it, but better to do that so we can in future decide > to take advantage of it. I definitely have plans for this feature right now, as some of the traps that KVM uses could be minimised using FGT, so I don't believe the feature will stay unused for too long. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel