From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE2A8C001B0 for ; Tue, 15 Aug 2023 10:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8H7fm7JYmH77UjEklTRKTlhyQ2Mo4sZdh0gDwsSdf1U=; b=C8LBRJCHJS2cTK 1OZeIu+xFCBqXh6vpcFNTYPmnuI8PDvf3gQQ8gKOMj6tDU5xaWRiJ9V3A5YPz1mnh1xY8xj4/j4Av 18Oo6vy2Fdy5e5KmoySOE+1Xfo5/eSU+9k6VxGmdvbNkI25/DLOe9JoUxFOoQfzv0+e0gKzwrftlx O8XNiCunj6DOVNmMekTFZ9LVZauorZXVs5JuFutwSJ/F5cFwOnn74ttFH23b1Xlwhx5MDqiUEQGIn N9JUYLRnEaoBgZ2WDLO3dgzys7V9IPPTsn65USh1dgCq4JWnrqqIJMXWg2ITi1mwd25NDoL5Ku3SV Eob5Vlt95dMRg6PNi9OQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qVrS3-001Iqu-2j; Tue, 15 Aug 2023 10:39:03 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qVrS0-001Iq9-2h for linux-arm-kernel@lists.infradead.org; Tue, 15 Aug 2023 10:39:02 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2B9EE6192E; Tue, 15 Aug 2023 10:38:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 456A7C433C8; Tue, 15 Aug 2023 10:38:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692095937; bh=zda4u5KUJ4HH3d/gEyOAJ3iuNxo/s4/E3XJ7jsuJk88=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XM1DkbFYFoG9FobSob7KV0gsgLlrZJ6xQKWTqoVVxaYbLmSf90NjsF9eHVA5UMI/K eUDQq3SYB2qYIrDjPtZt5DokmGIbrQHcCESyC45nqg4OX8f5Iq+wxqW2yQAEGcYZU9 my4dSjM5Xkd6H/DFQtdai1YE9kqN04efXtbJLrRpoYghMWq0HkrkuDKITHuUNTUV7T GduSrlNjmVj+NDgx4aADksZiJGbaHislJ0e9JDJ7s591x5MFrJx25RXasAS6rg7NDg C40wsBXJZcKfus9hMmY/EbUPS9PMRnZml85NOXcqaRzrgsyTWKowrz5TGmsyo7ae6G MDok11H3ZA4QA== Received: from host213-123-75-60.in-addr.btopenworld.com ([213.123.75.60] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qVrRv-004yal-3P; Tue, 15 Aug 2023 11:38:55 +0100 Date: Tue, 15 Aug 2023 11:39:07 +0100 Message-ID: <87il9gpp2s.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Catalin Marinas , Eric Auger , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v3 15/27] KVM: arm64: nv: Add trap forwarding for HCR_EL2 In-Reply-To: <85C2D540-7AD7-49BB-9EFB-7F950D08AC15@oracle.com> References: <20230808114711.2013842-1-maz@kernel.org> <20230808114711.2013842-16-maz@kernel.org> <85C2D540-7AD7-49BB-9EFB-7F950D08AC15@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 213.123.75.60 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, eric.auger@redhat.com, broonie@kernel.org, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230815_033900_963594_DEDC15CC X-CRM114-Status: GOOD ( 30.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Miguel, On Sat, 12 Aug 2023 04:08:22 +0100, Miguel Luis wrote: > > Hi Marc, > > > On 8 Aug 2023, at 11:46, Marc Zyngier wrote: > > > > Describe the HCR_EL2 register, and associate it with all the sysregs > > it allows to trap. > > > > Reviewed-by: Eric Auger > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/emulate-nested.c | 486 ++++++++++++++++++++++++++++++++ > > 1 file changed, 486 insertions(+) > > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > index 1b1148770d45..2122d16bdeeb 100644 > > --- a/arch/arm64/kvm/emulate-nested.c > > +++ b/arch/arm64/kvm/emulate-nested.c > > @@ -37,12 +37,48 @@ enum trap_group { > > * on their own instead of being part of a combination of > > * trap controls. > > */ > > + CGT_HCR_TID1, > > + CGT_HCR_TID2, > > + CGT_HCR_TID3, > > + CGT_HCR_IMO, > > + CGT_HCR_FMO, > > + CGT_HCR_TIDCP, > > + CGT_HCR_TACR, > > + CGT_HCR_TSW, > > + CGT_HCR_TPC, > > + CGT_HCR_TPU, > > + CGT_HCR_TTLB, > > + CGT_HCR_TVM, > > + CGT_HCR_TDZ, > > + CGT_HCR_TRVM, > > + CGT_HCR_TLOR, > > + CGT_HCR_TERR, > > + CGT_HCR_APK, > > + CGT_HCR_NV, > > + CGT_HCR_NV_nNV2, > > + CGT_HCR_NV1_nNV2, > > + CGT_HCR_AT, > > + CGT_HCR_FIEN, > > + CGT_HCR_TID4, > > + CGT_HCR_TICAB, > > + CGT_HCR_TOCU, > > + CGT_HCR_ENSCXT, > > + CGT_HCR_TTLBIS, > > + CGT_HCR_TTLBOS, > > > > /* > > * Anything after this point is a combination of trap controls, > > * which all must be evaluated to decide what to do. > > */ > > __MULTIPLE_CONTROL_BITS__, > > + CGT_HCR_IMO_FMO = __MULTIPLE_CONTROL_BITS__, > > + CGT_HCR_TID2_TID4, > > + CGT_HCR_TTLB_TTLBIS, > > + CGT_HCR_TTLB_TTLBOS, > > + CGT_HCR_TVM_TRVM, > > + CGT_HCR_TPU_TICAB, > > + CGT_HCR_TPU_TOCU, > > + CGT_HCR_NV1_nNV2_ENSCXT, > > > > /* > > * Anything after this point requires a callback evaluating a > > @@ -55,6 +91,174 @@ enum trap_group { > > }; > > > > static const struct trap_bits coarse_trap_bits[] = { > > + [CGT_HCR_TID1] = { > > + .index = HCR_EL2, > > + .value = HCR_TID1, > > + .mask = HCR_TID1, > > + .behaviour = BEHAVE_FORWARD_READ, > > + }, > > + [CGT_HCR_TID2] = { > > + .index = HCR_EL2, > > + .value = HCR_TID2, > > + .mask = HCR_TID2, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TID3] = { > > + .index = HCR_EL2, > > + .value = HCR_TID3, > > + .mask = HCR_TID3, > > + .behaviour = BEHAVE_FORWARD_READ, > > + }, > > + [CGT_HCR_IMO] = { > > + .index = HCR_EL2, > > + .value = HCR_IMO, > > + .mask = HCR_IMO, > > + .behaviour = BEHAVE_FORWARD_WRITE, > > + }, > > + [CGT_HCR_FMO] = { > > + .index = HCR_EL2, > > + .value = HCR_FMO, > > + .mask = HCR_FMO, > > + .behaviour = BEHAVE_FORWARD_WRITE, > > + }, > > + [CGT_HCR_TIDCP] = { > > + .index = HCR_EL2, > > + .value = HCR_TIDCP, > > + .mask = HCR_TIDCP, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TACR] = { > > + .index = HCR_EL2, > > + .value = HCR_TACR, > > + .mask = HCR_TACR, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TSW] = { > > + .index = HCR_EL2, > > + .value = HCR_TSW, > > + .mask = HCR_TSW, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TPC] = { /* Also called TCPC when FEAT_DPB is implemented */ > > + .index = HCR_EL2, > > + .value = HCR_TPC, > > + .mask = HCR_TPC, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TPU] = { > > + .index = HCR_EL2, > > + .value = HCR_TPU, > > + .mask = HCR_TPU, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TTLB] = { > > + .index = HCR_EL2, > > + .value = HCR_TTLB, > > + .mask = HCR_TTLB, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TVM] = { > > + .index = HCR_EL2, > > + .value = HCR_TVM, > > + .mask = HCR_TVM, > > + .behaviour = BEHAVE_FORWARD_WRITE, > > + }, > > + [CGT_HCR_TDZ] = { > > + .index = HCR_EL2, > > + .value = HCR_TDZ, > > + .mask = HCR_TDZ, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TRVM] = { > > + .index = HCR_EL2, > > + .value = HCR_TRVM, > > + .mask = HCR_TRVM, > > + .behaviour = BEHAVE_FORWARD_READ, > > + }, > > + [CGT_HCR_TLOR] = { > > + .index = HCR_EL2, > > + .value = HCR_TLOR, > > + .mask = HCR_TLOR, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_TERR] = { > > + .index = HCR_EL2, > > + .value = HCR_TERR, > > + .mask = HCR_TERR, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_APK] = { > > + .index = HCR_EL2, > > + .value = 0, > > + .mask = HCR_APK, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_NV] = { > > + .index = HCR_EL2, > > + .value = HCR_NV, > > + .mask = HCR_NV, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_NV_nNV2] = { > > + .index = HCR_EL2, > > + .value = HCR_NV, > > + .mask = HCR_NV | HCR_NV2, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > + [CGT_HCR_NV1_nNV2] = { > > + .index = HCR_EL2, > > + .value = HCR_NV | HCR_NV1, > > + .mask = HCR_NV | HCR_NV1 | HCR_NV2, > > + .behaviour = BEHAVE_FORWARD_ANY, > > + }, > > The declaration above seems to be a coarse control combination that could be > decomposed in the following, more readable, equivalent by adding a > combination of two MCBs > (eg. CGT_HCR_NV_NV1, CGT_HCR_NV_NV1_nNV2) > > [CGT_HCR_NV1] = { > .index = HCR_EL2, > .value = HCR_NV1, > .mask = HCR_NV1, > .behaviour = BEHAVE_FORWARD_ANY, > }, > [CGT_HCR_NV1_nNV2] = { > .index = HCR_EL2, > .value = HCR_NV1, > .mask = HCR_NV1 | HCR_NV2, > .behaviour = BEHAVE_FORWARD_ANY, > }, > > /* FEAT_NV and FEAT_NV2 */ > MCB(CGT_HCR_NV_NV1, CGT_HCR_NV, CGT_HCR_NV1) > > /* FEAT_NV2 and HCR_EL2.NV2 is 0 behaves as FEAT_NV */ > MCB(CGT_HCR_NV_NV1_nNV2, CGT_HCR_NV_nNV2, CGT_HCR_NV1_nNV2 ) This is not equivalent at all, as a MCB is a logical OR, not an AND. > On the above all the coarse HCR_EL2.{NV,NV1} traps are covered but not the > constrained unpredictable one when HCR_EL2.{NV,NV1} is {0,1} which traps in > two of its behaviours and doesn't trap on one. The current approach makes it plain that HCR_EL2.NV==0 doesn't result in any trap forwarding, consistent with the current wording of architecture. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel