Re: [PATCH 3/3] KVM: arm64: selftests: arch_timer_edge_cases - workaround for AC03_CPU_14

[Marc Zyngier <maz@kernel.org>]

On Fri, 09 May 2025 15:33:12 +0100,
Sebastian Ott <sebott@redhat.com> wrote:
> 
> arch_timer_edge_cases currently fails on ampere-one machines with
> the following assertion failure:
> 
> ==== Test Assertion Failure ====
>   arm64/arch_timer_edge_cases.c:169: timer_condition == istatus
>   pid=11236 tid=11236 errno=4 - Interrupted system call
>      1  0x0000000000404ce7: test_run at arch_timer_edge_cases.c:938
>      2  0x0000000000401ebb: main at arch_timer_edge_cases.c:1053
>      3  0x0000ffff9fa8625b: ?? ??:0
>      4  0x0000ffff9fa8633b: ?? ??:0
>      5  0x0000000000401fef: _start at ??:?
>   0x1 != 0x0 (timer_condition != istatus)
> 
> Meaning that the timer condition was met and an interrupt
> was presented but the timer status bit in the control register
> was not set.
> 
> This happens due to AC03_CPU_14 "Timer CVAL programming of a delta
> greater than 2^63 will result in incorrect behavior."
> 
> Work around this issue by reducing the value that is used to reset
> the counter and thus reduce the delta.
> 
> Link: https://lore.kernel.org/kvmarm/ac1de1d2-ef2b-d439-dc48-8615e121b07b@redhat.com
> Link: https://amperecomputing.com/assets/AmpereOne_Developer_ER_v0_80_20240823_28945022f4.pdf
> Signed-off-by: Sebastian Ott <sebott@redhat.com>
> ---
>  tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
> index a813b4c6c817..2f0397df0aa6 100644
> --- a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
> +++ b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
> @@ -31,7 +31,7 @@ static const int32_t TVAL_MIN = INT32_MIN;
>  static const uint32_t TIMEOUT_NO_IRQ_US = 50000;
>  
>  /* A nice counter value to use as the starting one for most tests. */
> -static const uint64_t DEF_CNT = (CVAL_MAX / 2);
> +static const uint64_t DEF_CNT = (CVAL_MAX / 4);

This is rather arbitrary, and only sidestep the issue: the core
problem is that CVAL_MAX is defined as ~0, and that we have no idea
what the *effective* counter width is.

So while this happen to sidestep the particular Ampere erratum (and
avoid failures on X1E), this is only papering over the problem. Which
is why I always had some reservations on this particular test -- it is
remarkably broken.

If anything, we should compute the expected width of the counter based
on the frequency and the architectural guarantees ("Roll-over time of
not less than 40 years."), just like the kernel driver does (see
arch_counter_get_width()).

I'm also not keen on hiding a HW bug by altering the test. What of
other guests that would fall into the same issue? If we think the
problem exposed by this test is serious enough, then we need to fully
trap and emulate the timers, X1E style. Performance would definitely
suffer, but that would be the correct thing to do.

So my proposal is to fix the test to be compliant with the intent of
the architecture instead of making bets and using semi-random values.
If that's good enough to make that test pass on A1, great.

Thanks,

	M.

-- 
Jazz isn't dead. It just smells funny.