From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DA42C3DA4A for ; Tue, 20 Aug 2024 16:37:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: Message-ID:Date:References:In-Reply-To:Subject:Cc:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tXxjzfNvXa7meJpazSZNQQ8FpcQnTXtyOsktI6sRWEI=; b=1vAuVagivXQvgucywbwft5Zswb 4lBbrdy0w1LrXniByXAYJRH5rPAR+mjZzCjCGgzVHuI0ZK7Gx/4J3JZFx9KYFcnPuZg1iXQrrJ+G6 XkK4D8ZYLV+g+SW18DcFIG78VHbWFcRCzfy2tr8RN2iFNWYr5C5Np3UaFKMuk7z1PVvuIMAEuFyMR MW1T8qFUwtvBLjsnyi/o5oC13zvexGuCcP2KmfCzS8A6nLSQNT5Y60KsPfTMafdCSuLZnVQnb08gW UboUYtwAdf464O/fMUSlvYBNrzT9kJQCrdraXkMXUnqhacKE9FvOjQ0t/1gPQlxqFJxBf84EU66X2 o9Z9Pv7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgRqw-000000061rs-0kdj; Tue, 20 Aug 2024 16:37:02 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgRq9-000000061c1-2QbY for linux-arm-kernel@lists.infradead.org; Tue, 20 Aug 2024 16:36:17 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1724171770; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=tXxjzfNvXa7meJpazSZNQQ8FpcQnTXtyOsktI6sRWEI=; b=akgMHrmfiVyofrjgjnqbLNfWzqN0ZWvBO0uC5Tpq+/W2Rj+vlWsRlFJcjS8DMGoqMF57EV pfayzAWAApR2aVZ7YGjvzSHn6PEx1XNZKqYpPRhu2B0aSkWdswXqOwDXrsY3YIsSP13qDB HBOqWyCjb7EUGbnhfqvL3Jcx3+e5ArCGuXfNYHYNOZNX0/lN0HJgrCCYdWsKBoaiyNaDzd S4WEhlKe1+jlSARpSl7XulsHVUBNYpYRkUnooBlEZ2nsc7QW1tZnGkf8QxCjLE/herX0TL ycoJeV8aUK7PjoESHhpZmZ4ym7mnQVtoieYiE1s1kXZBHiZbegD0E2CP2bA8Qg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1724171770; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=tXxjzfNvXa7meJpazSZNQQ8FpcQnTXtyOsktI6sRWEI=; b=iC1vjxcKHrTmZyblav6TqDJEu2J3hR2Qvg8lP7+ALNVpc8X9cROBkScrCqv+rtiw+0u79M uwLtVKzL6cbzH9BA== To: Mark Rutland , linux-arm-kernel@lists.infradead.org Cc: alexandru.elisei@arm.com, andre.przywara@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, will@kernel.org Subject: Re: [PATCH] irqchip/gic-v3: init SRE before poking sysregs In-Reply-To: <20240820155506.100164-1-mark.rutland@arm.com> References: <20240820155506.100164-1-mark.rutland@arm.com> Date: Tue, 20 Aug 2024 18:36:10 +0200 Message-ID: <87jzgbjgn9.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240820_093613_928985_44E41D3E X-CRM114-Status: GOOD ( 17.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Aug 20 2024 at 16:55, Mark Rutland wrote: > The GICv3 driver pokes GICv3 system registers in gic_prio_init() before > gic_cpu_sys_reg_init() ensures that SRE has been initialized. On arm64 > the architecture code will have initialized ZRE prior to this, but on > 32-bit ARM that is not the case, and consequently in gic_prio_init() the > system register accesses may result in an UNDEF. > > This is a regression introduced by commit: > > d447bf09a4013541 ("irqchip/gic-v3: Detect GICD_CTRL.DS and SCR_EL3.FIQ earlier") > > ... which added gic_prio_init(). That's already clear from the fixes tag, no? > This has been observed to result in boot failures when booting a 32-bit > kernel on an FVP using the boot-wrapper, e.g. > > | Internal error: Oops - undefined instruction: 0 [#1] SMP ARM > | Modules linked in: > | CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.11.0-rc3-00002-g102b1595b998 #6 > | Hardware name: ARM-Versatile Express > | PC is at gic_init_bases+0x378/0x76c > | LR is at gic_init_bases+0x30c/0x76c > | pc : [] lr : [] psr: 600000d3 > | sp : c1c01e18 ip : 00000000 fp : 00000001 > | r10: 2f000000 r9 : c1ebcc68 r8 : 00000000 > | r7 : c1c097c0 r6 : c17adae0 r5 : eeff7edc r4 : c1c05af8 > | r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 0000001e > | Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none > | Control: 10c0383d Table: 8020406a DAC: 00000051 > | Register r0 information: non-paged memory > | Register r1 information: NULL pointer > | Register r2 information: NULL pointer > | Register r3 information: NULL pointer > | Register r4 information: non-slab/vmalloc memory > | Register r5 information: non-slab/vmalloc memory > | Register r6 information: non-slab/vmalloc memory > | Register r7 information: non-slab/vmalloc memory > | Register r8 information: NULL pointer > | Register r9 information: non-slab/vmalloc memory > | Register r10 information: non-paged memory > | Register r11 information: non-paged memory > | Register r12 information: NULL pointer > | Process swapper/0 (pid: 0, stack limit = 0x(ptrval)) > | Stack: (0xc1c01e18 to 0xc1c02000) > | 1e00: c0207c28 2f280000 > | 1e20: f0a7ffff ffe00000 fffff000 eeff7edc 00000000 00000000 ffffffff 00000000 > | 1e40: 00000000 c133cd3c c1c05b00 00000000 00000000 00000000 00000000 c2092410 > | 1e60: c17d615c c04b6710 ff800000 00200000 00000000 f0880000 ff8024c8 eeff7f5c > | 1e80: c17d6280 c0f90b00 c1ee1434 a00000d3 eeff7ed0 c17d6280 00000001 c2092410 > | 1ea0: c17d615c 00000000 c133cd24 eeff7ed0 2f000000 f0820000 c2092400 00000001 > | 1ec0: c2092410 c17d615c 00000001 c1a34db8 00000000 00000000 eeff7edc c17d7e84 > | 1ee0: c1c01efc 00000001 00000000 00000000 00000000 2f100000 2f2fffff eeff7f3c > | 1f00: 00000200 00000000 00000000 00000000 00000000 c0f90aec c1b55078 00000000 > | 1f20: 00000000 c1b5513c 00000000 00000000 00000000 00000000 c1c01f6c c2092340 > | 1f40: 00000000 c1c01f6c c1c01f74 c1c01f6c 00000122 00000100 c18183d8 c1aa489c > | 1f60: 00000000 00000007 00000000 c1c01f6c c1c01f6c c1c01f74 c1c01f74 00000000 > | 1f80: 00000000 c1acfa50 c1b5a000 c191b3c8 c1a0100c efffee00 00000000 00000038 > | 1fa0: 00000000 c1a03fd0 c1a0100c c1a1f6cc 00000000 c1e7c000 c19196d8 00000000 > | 1fc0: c1c04e00 c1a0100c ffffffff ffffffff 00000000 c1a006ec 00000000 00000000 > | 1fe0: 00000000 c1acfa60 00000000 ffffffff 00000000 00000000 00000000 00000000 In which way is all of this OOPS gunk useful to describe the problem? https://www.kernel.org/doc/html/latest/process/submitting-patches.html#backtraces > | Call trace: > | gic_init_bases from gic_of_init+0x1c0/0x29c > | gic_of_init from of_irq_init+0x1d4/0x324 > | of_irq_init from init_IRQ+0xa8/0x108 > | init_IRQ from start_kernel+0x540/0x6b8 > | start_kernel from 0x0 This is really the only relevant information if at all, no? > | Code: e2033040 e3530000 13a01001 03a01000 (ee140f16) > | ---[ end trace 0000000000000000 ]--- > | Kernel panic - not syncing: Attempted to kill the idle task! > | ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- > > Fix this by factoring out the SRE initialization into a new > gic_sre_init(), and calling this in the early in the three paths where calling this in the early ? > SRE may not have been initialized: > > (1) gic_init_bases(), before the primary CPU pokes GICv3 sysregs in > gic_prio_init(). > > (2) gic_starting_cpu(), before secondary CPUs initialize GICv3 sysregs > in gic_cpu_init(). > > (3) gic_cpu_pm_notifier(), before CPUs re-initialize GICv3 sysregs in > gic_cpu_sys_reg_init(). Thanks, tglx