From: Marc Zyngier <maz@kernel.org>
To: Florian Fainelli <florian.fainelli@broadcom.com>
Cc: linux-kernel@vger.kernel.org, Doug Berger <opendmb@gmail.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>,
Thomas Gleixner <tglx@linutronix.de>,
Brian Norris <computersforpeace@gmail.com>,
Jason Cooper <jason@lakedaemon.net>,
linux-mips@vger.kernel.org (open list:BROADCOM BMIPS MIPS
ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM7XXX ARM ARCHITECTURE)
Subject: Re: [PATCH v2] irqchip/irq-brcmstb-l2: add write memory barrier before exit
Date: Sat, 10 Feb 2024 09:32:21 +0000 [thread overview]
Message-ID: <87jzncwtp6.wl-maz@kernel.org> (raw)
In-Reply-To: <20240210012449.3009125-1-florian.fainelli@broadcom.com>
On Sat, 10 Feb 2024 01:24:49 +0000,
Florian Fainelli <florian.fainelli@broadcom.com> wrote:
>
> From: Doug Berger <opendmb@gmail.com>
>
> It was observed on Broadcom devices that use GIC v3 architecture
> L1 interrupt controllers as the parent of brcmstb-l2 interrupt
> controllers that the deactivation of the parent irq could happen
> before the brcmstb-l2 deasserted its output. This would lead the
> GIC to reactivate the irq only to find that no L2 interrupt was
> pending. The result was a spurious interrupt invoking the
> handle_bad_irq() with its associated messaging. While this did
> not create a functional problem it is a waste of cycles.
>
> The hazard exists because the memory mapped bus writes to the
> brcmstb-l2 registers are buffered and the GIC v3 architecture
> uses a very efficient system register write to deactivate the
> interrupt. This commit adds a write memory barrier prior to
> invoking chained_irq_exit() to introduce a dsb(st) on those
> systems to ensure the system register write cannot be executed
> until the memory mapped writes are visible to the system.
>
> Signed-off-by: Doug Berger <opendmb@gmail.com>
> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
> Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller")
> [florian: Added Fixes tag]
> Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
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prev parent reply other threads:[~2024-02-10 9:32 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-10 1:24 [PATCH v2] irqchip/irq-brcmstb-l2: add write memory barrier before exit Florian Fainelli
2024-02-10 9:32 ` Marc Zyngier [this message]
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