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Thu, 27 Jul 2023 14:12:17 +0100 Date: Thu, 27 Jul 2023 14:12:16 +0100 Message-ID: <87jzulqz0v.wl-maz@kernel.org> From: Marc Zyngier To: Raghavendra Rao Ananta Cc: Oliver Upton , James Morse , Suzuki K Poulose , Paolo Bonzini , Sean Christopherson , Huacai Chen , Zenghui Yu , Anup Patel , Atish Patra , Jing Zhang , Reiji Watanabe , Colton Lewis , David Matlack , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v7 12/12] KVM: arm64: Use TLBI range-based intructions for unmap In-Reply-To: <20230722022251.3446223-13-rananta@google.com> References: <20230722022251.3446223-1-rananta@google.com> <20230722022251.3446223-13-rananta@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 104.132.45.102 X-SA-Exim-Rcpt-To: rananta@google.com, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, seanjc@google.com, chenhuacai@kernel.org, yuzenghui@huawei.com, anup@brainfault.org, atishp@atishpatra.org, jingzhangos@google.com, reijiw@google.com, coltonlewis@google.com, dmatlack@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230727_061220_788488_F74D18FA X-CRM114-Status: GOOD ( 31.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 22 Jul 2023 03:22:51 +0100, Raghavendra Rao Ananta wrote: > > The current implementation of the stage-2 unmap walker traverses > the given range and, as a part of break-before-make, performs > TLB invalidations with a DSB for every PTE. A multitude of this > combination could cause a performance bottleneck on some systems. > > Hence, if the system supports FEAT_TLBIRANGE, defer the TLB > invalidations until the entire walk is finished, and then > use range-based instructions to invalidate the TLBs in one go. > Condition deferred TLB invalidation on the system supporting FWB, > as the optimization is entirely pointless when the unmap walker > needs to perform CMOs. > > Rename stage2_put_pte() to stage2_unmap_put_pte() as the function > now serves the stage-2 unmap walker specifically, rather than > acting generic. > > Signed-off-by: Raghavendra Rao Ananta > --- > arch/arm64/kvm/hyp/pgtable.c | 67 +++++++++++++++++++++++++++++++----- > 1 file changed, 58 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > index 5ef098af1736..cf88933a2ea0 100644 > --- a/arch/arm64/kvm/hyp/pgtable.c > +++ b/arch/arm64/kvm/hyp/pgtable.c > @@ -831,16 +831,54 @@ static void stage2_make_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t n > smp_store_release(ctx->ptep, new); > } > > -static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, > - struct kvm_pgtable_mm_ops *mm_ops) > +struct stage2_unmap_data { > + struct kvm_pgtable *pgt; > + bool defer_tlb_flush_init; > +}; > + > +static bool __stage2_unmap_defer_tlb_flush(struct kvm_pgtable *pgt) > +{ > + /* > + * If FEAT_TLBIRANGE is implemented, defer the individual > + * TLB invalidations until the entire walk is finished, and > + * then use the range-based TLBI instructions to do the > + * invalidations. Condition deferred TLB invalidation on the > + * system supporting FWB, as the optimization is entirely > + * pointless when the unmap walker needs to perform CMOs. > + */ > + return system_supports_tlb_range() && stage2_has_fwb(pgt); > +} > + > +static bool stage2_unmap_defer_tlb_flush(struct stage2_unmap_data *unmap_data) > +{ > + bool defer_tlb_flush = __stage2_unmap_defer_tlb_flush(unmap_data->pgt); > + > + /* > + * Since __stage2_unmap_defer_tlb_flush() is based on alternative > + * patching and the TLBIs' operations behavior depend on this, > + * track if there's any change in the state during the unmap sequence. > + */ > + WARN_ON(unmap_data->defer_tlb_flush_init != defer_tlb_flush); > + return defer_tlb_flush; I really don't understand what you're testing here. The ability to defer TLB invalidation is a function of the system capabilities (range+FWB) and a single flag that is only set on the host for pKVM. How could that change in the middle of the life of the system? if further begs the question about the need for the unmap_data data structure. It looks to me that we could simply pass the pgt pointer around and be done with it. Am I missing something obvious? M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel