From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A885EC433EF for ; Tue, 12 Oct 2021 08:33:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 751AB60EE5 for ; Tue, 12 Oct 2021 08:33:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 751AB60EE5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pOdAQtJRjJbFjFxMLPlQAXyV5HdXoiyNhyeD0ftTTeU=; b=jlQPOsZtFeUYJJ xKsma3+SMgK+nYgnMCICzNJ0lH81jI0mkxCeELCB2/fO+KD+NUFi1EoKQSVBfaSKFJ6bsZRxnRq5L aSFhgZvogX2cTStR20sUUlV0nOUIpCE6UU9XTROQNusLnrbmh3VcEzmoh6U2a/0LSt9d9AQAF9G/E hyPQ+UhEAjr/2DjYTO900KwNYpWvCJijY722qz1wEWP8EMz3s/8xdPRe1MKowZK6NPPQ9eqKWMvPk y/gvYQ0Ap3sQowHLaGHI7jjSP8cd3iLhFYxLVZHDz6coODByu7mteikhj59h2UR+yUt3pINqQceta iJ89vf1Tf2so6vKIsDVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1maDBH-00C0rj-Do; Tue, 12 Oct 2021 08:30:39 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1maDAp-00C0hC-EB for linux-arm-kernel@lists.infradead.org; Tue, 12 Oct 2021 08:30:13 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 195FD60E74; Tue, 12 Oct 2021 08:30:11 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1maDAn-00GCnq-15; Tue, 12 Oct 2021 09:30:09 +0100 Date: Tue, 12 Oct 2021 09:30:08 +0100 Message-ID: <87k0iiprvz.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, steven.price@arm.com Subject: Re: [RFC V3 13/13] KVM: arm64: Enable FEAT_LPA2 based 52 bits IPA size on 4K and 16K In-Reply-To: References: <1632998116-11552-1-git-send-email-anshuman.khandual@arm.com> <1632998116-11552-14-git-send-email-anshuman.khandual@arm.com> <87r1crq32z.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, steven.price@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_013011_558293_BF1C529B X-CRM114-Status: GOOD ( 44.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 12 Oct 2021 05:24:15 +0100, Anshuman Khandual wrote: > > Hello Marc, > > On 10/11/21 3:46 PM, Marc Zyngier wrote: > > On Thu, 30 Sep 2021 11:35:16 +0100, > > Anshuman Khandual wrote: > >> > >> Stage-2 FEAT_LPA2 support is independent and also orthogonal to FEAT_LPA2 > >> support either in Stage-1 or in the host kernel. Stage-2 IPA range support > >> is evaluated from the platform via ID_AA64MMFR0_TGRAN_2_SUPPORTED_LPA2 and > >> gets enabled regardless of Stage-1 translation. > >> > >> Signed-off-by: Anshuman Khandual > >> --- > >> arch/arm64/include/asm/kvm_pgtable.h | 10 +++++++++- > >> arch/arm64/kvm/hyp/pgtable.c | 25 +++++++++++++++++++++++-- > >> arch/arm64/kvm/reset.c | 14 ++++++++++---- > >> 3 files changed, 42 insertions(+), 7 deletions(-) > >> > >> diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > >> index 0277838..78a9d12 100644 > >> --- a/arch/arm64/include/asm/kvm_pgtable.h > >> +++ b/arch/arm64/include/asm/kvm_pgtable.h > >> @@ -29,18 +29,26 @@ typedef u64 kvm_pte_t; > >> > >> #define KVM_PTE_ADDR_MASK GENMASK(47, PAGE_SHIFT) > >> #define KVM_PTE_ADDR_51_48 GENMASK(15, 12) > >> +#define KVM_PTE_ADDR_51_50 GENMASK(9, 8) > >> > >> static inline bool kvm_pte_valid(kvm_pte_t pte) > >> { > >> return pte & KVM_PTE_VALID; > >> } > >> > >> +void set_kvm_lpa2_enabled(void); > >> +bool get_kvm_lpa2_enabled(void); > >> + > >> static inline u64 kvm_pte_to_phys(kvm_pte_t pte) > >> { > >> u64 pa = pte & KVM_PTE_ADDR_MASK; > >> > >> - if (PAGE_SHIFT == 16) > >> + if (PAGE_SHIFT == 16) { > >> pa |= FIELD_GET(KVM_PTE_ADDR_51_48, pte) << 48; > >> + } else { > >> + if (get_kvm_lpa2_enabled()) > > > > Having to do a function call just for this test seems bad, specially > > for something that is used so often on the fault path. > > > > Why can't this be made a normal capability that indicates LPA support > > for the current page size? > > Although I could look into making this a normal capability check, would > not a static key based implementation be preferred if the function call > based construct here is too expensive ? A capability *is* a static key. Specially if you make it final. > Originally, avoided capability method for stage-2 because it would have > been difficult in stage-1 where the FEAT_LPA2 detection is required way > earlier during boot before cpu capability comes up. Hence just followed > a simple variable method both for stage-1 and stage-2 keeping it same. I think you'll have to find a way to make it work with a capability for S1 too. Capabilities can be used even when not final, and you may have to do something similar. > > > >> + pa |= FIELD_GET(KVM_PTE_ADDR_51_50, pte) << 50; > > > > Where are bits 48 and 49? > > Unlike the current FEAT_LPA feature, bits 48 and 49 are part of the PA > itself. Only the bits 50 and 51 move into bits 8 and 9, while creating > a PTE. So why are you actively dropping these bits? Hint: look at KVM_PTE_ADDR_MASK and the way it is used to extract the initial value of 'pa'. [...] > > Another thing I don't see is how you manage TLB invalidation by level > > now that we gain a level 0 at 4kB, breaking the current assumptions > > encoded in __tlbi_level(). > > Right, I guess something like this (not build tested) will be required as > level 0 for 4K and level 1 for 16K would only make sense when FEAT_LPA2 is > implemented, otherwise it will fallback to the default behaviour i.e table > level hint was not provided (TTL[3:2] is 0b00). Is there any other concern > which I might be missing here ? > > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -104,8 +104,7 @@ static inline unsigned long get_trans_granule(void) > #define __tlbi_level(op, addr, level) do { \ > u64 arg = addr; \ > \ > - if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ > - level) { \ > + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) { \ > u64 ttl = level & 3; \ > ttl |= get_trans_granule() << 2; \ > arg &= ~TLBI_TTL_MASK; \ > That's a start, but 0 has always meant 'at any level' until now. You will have to audit all the call sites and work out whether they can pass 0 if they don't track the actual level. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel