From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D834EC4338F for ; Mon, 9 Aug 2021 18:04:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83025601FC for ; Mon, 9 Aug 2021 18:04:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 83025601FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m9pglPKrkUYsZMty8BzLfc0rF6tpu6FRYADxpmo2H3E=; b=TzGI+dkTvCXVDE p/wiNCtolZz2HUFZd+QOjI1GMyQSDLSQlFGaSRdMmj91NUhVdeiUUDEhhsdfhSwp2Qqh0v+jDbbIu lLP6uPdZBO4sNYYiS+3EJkImLRUaqkGUTKrW1bR+1FzkVK0wN1QE+pef3Z4VXpZme6GYcJOgI0MsO 5JCFSCexPy6ez0N0qXRjYlZAHLbT6tDV8c1zs8/p2nQs0E5Zjuapm0Hv8vJvu1texg5Vq+VWHnnhC eIQZui2/3V38Eyj61bpoVqajIUZkMvrvnm0UVzOS1bSKg5k/sH2qm09CSt3C2vlaWIuP+nRLvyWGd kldClPpNQ6abXPvRSfoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD9bj-001dLs-N8; Mon, 09 Aug 2021 18:02:39 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mD9bg-001dLT-0I for linux-arm-kernel@lists.infradead.org; Mon, 09 Aug 2021 18:02:37 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B33D8610EA; Mon, 9 Aug 2021 18:02:35 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mD9bd-003sZZ-Mp; Mon, 09 Aug 2021 19:02:33 +0100 Date: Mon, 09 Aug 2021 19:02:33 +0100 Message-ID: <87k0kubio6.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Will Deacon , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: Re: [PATCH 12/13] arm64: Add a capability for FEAT_EVC In-Reply-To: References: <20210809152651.2297337-1-maz@kernel.org> <20210809152651.2297337-13-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, pshier@google.com, rananta@google.com, ricarkol@google.com, will@kernel.org, catalin.marinas@arm.com, linus.walleij@linaro.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210809_110236_118780_9016FD5C X-CRM114-Status: GOOD ( 29.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Oliver, Thanks for having a look. On Mon, 09 Aug 2021 17:30:45 +0100, Oliver Upton wrote: > > Hi Marc, > > On Mon, Aug 9, 2021 at 8:48 AM Marc Zyngier wrote: > > > > Add a new capability to detect the Enhanced Counter Virtualization > > feature (FEAT_EVC). > > > > s/FEAT_EVC/FEAT_ECV/g I'm the knig fo tpyoes :). > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > > arch/arm64/tools/cpucaps | 1 + > > 2 files changed, 11 insertions(+) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 0ead8bfedf20..9c2ce5408811 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -1899,6 +1899,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > .sign = FTR_UNSIGNED, > > .min_field_value = 1, > > }, > > + { > > + .desc = "Enhanced counter virtualization", > > + .capability = ARM64_HAS_ECV, > > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > + .matches = has_cpuid_feature, > > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > > + .sign = FTR_UNSIGNED, > > + .min_field_value = 1, > > + }, > > Per one of your other patches in the series, it sounds like userspace > access to the self-synchronized registers hasn't been settled yet. > However, if/when available to userspace, should this cpufeature map to > an ELF HWCAP? We can't prevent the access to userspace, unless we also trap cntvct_el0 and cntfreq_el0. Which we try not to do. But you are indeed correct, we probably have a HWCAP if we decide to advertise it to userspace. > Also, w.r.t. my series I have out for ECV in KVM. All the controls > used in EL2 depend on ECV=0x2. I agree that ECV=0x1 needs a cpufeature > bit, but what about EL2's use case? My idea was to have a ARM64_HAS_ECV2 to capture the EL2 extensions with min_field_value=2. > Besides the typo: > > Reviewed-by: Oliver Upton Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel