[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Baruch Siach]

The CP110 component has 4 uart peripherals. All of them use the same clock
gate for slow peripherals that is shared with the i2c and spi peripherals.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2: No change
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index a8af4136dbe7..a422cd981a0b 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -290,6 +290,46 @@
 			status = "disabled";
 		};
 
+		CP110_LABEL(uart0): serial at 702000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x702000 0x100>;
+			reg-shift = <2>;
+			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <1>;
+			clocks = <&CP110_LABEL(clk) 1 21>;
+			status = "disabled";
+		};
+
+		CP110_LABEL(uart1): serial at 702100 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x702100 0x100>;
+			reg-shift = <2>;
+			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <1>;
+			clocks = <&CP110_LABEL(clk) 1 21>;
+			status = "disabled";
+		};
+
+		CP110_LABEL(uart2): serial at 702200 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x702200 0x100>;
+			reg-shift = <2>;
+			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <1>;
+			clocks = <&CP110_LABEL(clk) 1 21>;
+			status = "disabled";
+		};
+
+		CP110_LABEL(uart3): serial at 702300 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x702300 0x100>;
+			reg-shift = <2>;
+			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <1>;
+			clocks = <&CP110_LABEL(clk) 1 21>;
+			status = "disabled";
+		};
+
 		CP110_LABEL(nand): nand at 720000 {
 			/*
 			* Due to the limitation of the pins available
-- 
2.15.1

[PATCH v2 2/2] arm64: dts: marvell: mcbin: enable uart headers

[Baruch Siach]

Add description of the J25 and J27 UART headers of the Macchiatobin. They use
uart peripherals that the CP0 (J25) and CP1 (J27) provide.

Even though J25 and J27 are labeled as UART header, the pins on these headers
can be muxed for other purposes. But the UART functionality is useful when the
board is mounted in an ATX style enclosure, since the console UART is not
accessible through the microUSB at CON9.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2:
  Add comments to indicate the headers board labels (Thomas)
  Explain in the commit log why we want the UART functionality (RMK)
---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 626e9d0462c3..122d2257ebc4 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -163,6 +163,13 @@
 	};
 };
 
+/* J25 UART header */
+&cp0_uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_uart1_pins>;
+	status = "okay";
+};
+
 &cp0_mdio {
 	pinctrl-names = "default";
 	pinctrl-0 = <&cp0_ge_mdio_pins>;
@@ -195,6 +202,10 @@
 		marvell,pins = "mpp37", "mpp38";
 		marvell,function = "i2c0";
 	};
+	cp0_uart1_pins: uart1-pins {
+		marvell,pins = "mpp40", "mpp41";
+		marvell,function = "uart1";
+	};
 	cp0_xhci_vbus_pins: xhci0-vbus-pins {
 		marvell,pins = "mpp47";
 		marvell,function = "gpio";
@@ -290,6 +301,17 @@
 		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
 		marvell,function = "spi1";
 	};
+	cp1_uart0_pins: uart0-pins {
+		marvell,pins = "mpp6", "mpp7";
+		marvell,function = "uart0";
+	};
+};
+
+/* J27 UART header */
+&cp1_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_uart0_pins>;
+	status = "okay";
 };
 
 &cp1_sata0 {
-- 
2.15.1

[PATCH v2 2/2] arm64: dts: marvell: mcbin: enable uart headers

[Gregory CLEMENT]

Hi Baruch,
 
 On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:

> Add description of the J25 and J27 UART headers of the Macchiatobin. They use
> uart peripherals that the CP0 (J25) and CP1 (J27) provide.
>
> Even though J25 and J27 are labeled as UART header, the pins on these headers
> can be muxed for other purposes. But the UART functionality is useful when the
> board is mounted in an ATX style enclosure, since the console UART is not
> accessible through the microUSB at CON9.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
> v2:
>   Add comments to indicate the headers board labels (Thomas)
>   Explain in the commit log why we want the UART functionality (RMK)
> ---
>  arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
> index 626e9d0462c3..122d2257ebc4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
> @@ -163,6 +163,13 @@
>  	};
>  };
>  
> +/* J25 UART header */
> +&cp0_uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_uart1_pins>;
> +	status = "okay";
> +};
> +
>  &cp0_mdio {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&cp0_ge_mdio_pins>;
> @@ -195,6 +202,10 @@
>  		marvell,pins = "mpp37", "mpp38";
>  		marvell,function = "i2c0";
>  	};
> +	cp0_uart1_pins: uart1-pins {
> +		marvell,pins = "mpp40", "mpp41";
> +		marvell,function = "uart1";
> +	};
>  	cp0_xhci_vbus_pins: xhci0-vbus-pins {
>  		marvell,pins = "mpp47";
>  		marvell,function = "gpio";
> @@ -290,6 +301,17 @@
>  		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
>  		marvell,function = "spi1";
>  	};
> +	cp1_uart0_pins: uart0-pins {
> +		marvell,pins = "mpp6", "mpp7";
> +		marvell,function = "uart0";
> +	};
> +};
> +
> +/* J27 UART header */
> +&cp1_uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp1_uart0_pins>;
> +	status = "okay";
>  };
>  
>  &cp1_sata0 {
> -- 
> 2.15.1
>

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Gregory CLEMENT]

Hi Baruch,
 
 On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:

> The CP110 component has 4 uart peripherals. All of them use the same clock
> gate for slow peripherals that is shared with the i2c and spi peripherals.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
> v2: No change
> ---
>  arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> index a8af4136dbe7..a422cd981a0b 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> @@ -290,6 +290,46 @@
>  			status = "disabled";
>  		};
>  
> +		CP110_LABEL(uart0): serial at 702000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702000 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart1): serial at 702100 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702100 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart2): serial at 702200 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702200 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart3): serial at 702300 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702300 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
>  		CP110_LABEL(nand): nand at 720000 {
>  			/*
>  			* Due to the limitation of the pins available
> -- 
> 2.15.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Gregory CLEMENT]

Hi Baruch,
 
 On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:

> The CP110 component has 4 uart peripherals. All of them use the same clock
> gate for slow peripherals that is shared with the i2c and spi peripherals.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
> v2: No change
> ---
>  arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> index a8af4136dbe7..a422cd981a0b 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> @@ -290,6 +290,46 @@
>  			status = "disabled";
>  		};
>  
> +		CP110_LABEL(uart0): serial at 702000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702000 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart1): serial at 702100 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702100 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart2): serial at 702200 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702200 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
> +		CP110_LABEL(uart3): serial at 702300 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x702300 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-io-width = <1>;
> +			clocks = <&CP110_LABEL(clk) 1 21>;
> +			status = "disabled";
> +		};
> +
>  		CP110_LABEL(nand): nand at 720000 {
>  			/*
>  			* Due to the limitation of the pins available
> -- 
> 2.15.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Baruch Siach]

Hi Gregory,

On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
>  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> 
> > The CP110 component has 4 uart peripherals. All of them use the same clock
> > gate for slow peripherals that is shared with the i2c and spi peripherals.
> >
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> 
> Applied on mvebu/dt64

Thanks.

What about patch 2/2 in this series?

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Gregory CLEMENT]

Hi Baruch,
 
 On mer., f?vr. 14 2018, Baruch Siach <baruch@tkos.co.il> wrote:

> Hi Gregory,
>
> On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
>>  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
>> 
>> > The CP110 component has 4 uart peripherals. All of them use the same clock
>> > gate for slow peripherals that is shared with the i2c and spi peripherals.
>> >
>> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>> 
>> Applied on mvebu/dt64
>
> Thanks.
>
> What about patch 2/2 in this series?

I thought I applied it, but now it's done.

Gregory

>
> baruch
>
> -- 
>      http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
>    - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Russell King - ARM Linux]

On Wed, Feb 14, 2018 at 12:56:53PM +0200, Baruch Siach wrote:
> Hi Gregory,
> 
> On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
> >  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> > 
> > > The CP110 component has 4 uart peripherals. All of them use the same clock
> > > gate for slow peripherals that is shared with the i2c and spi peripherals.
> > >
> > > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > 
> > Applied on mvebu/dt64
> 
> Thanks.
> 
> What about patch 2/2 in this series?

I'm not entirely convinced that it's something that should be done.
I know that some people are already using the UART headers for other
purposes (other than UART) and the later revision boards have the
placement of the microUSB fixed so it is accessible.

While you can tell Linux to use the other UART headers with this
patch, uboot won't use them, which means you can't configure the
boot loader without (in your case) taking the board out of the case.

I've a similar problem (with the mcbin in a rackmount case), and my
solution to that has been to put a single washer under the mounting
post near the microUSB to lift the board sufficiently to allow a
connector to be plugged in.  Sometimes simple hardware fixes are
better than software fixes.

Others have used a dremel to modify the case to access the microUSB.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Baruch Siach]

Hi Ressell,

On Wed, Feb 14, 2018 at 11:07:51AM +0000, Russell King - ARM Linux wrote:
> On Wed, Feb 14, 2018 at 12:56:53PM +0200, Baruch Siach wrote:
> > On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
> > >  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> > > 
> > > > The CP110 component has 4 uart peripherals. All of them use the same clock
> > > > gate for slow peripherals that is shared with the i2c and spi peripherals.
> > > >
> > > > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > > 
> > > Applied on mvebu/dt64
> > 
> > Thanks.
> > 
> > What about patch 2/2 in this series?
> 
> I'm not entirely convinced that it's something that should be done.
> I know that some people are already using the UART headers for other
> purposes (other than UART) and the later revision boards have the
> placement of the microUSB fixed so it is accessible.
> 
> While you can tell Linux to use the other UART headers with this
> patch, uboot won't use them, which means you can't configure the
> boot loader without (in your case) taking the board out of the case.
> 
> I've a similar problem (with the mcbin in a rackmount case), and my
> solution to that has been to put a single washer under the mounting
> post near the microUSB to lift the board sufficiently to allow a
> connector to be plugged in.  Sometimes simple hardware fixes are
> better than software fixes.
> 
> Others have used a dremel to modify the case to access the microUSB.

Just for the record, I'm fine with dropping 'status = "okay"' from the mcbin 
CP{0,1} UART nodes. This would still allow anyone who needs this functionality 
to enable it with a simple .dts modification, or a run-time dtb modification 
from the bootloader.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Russell King - ARM Linux]

On Wed, Feb 14, 2018 at 01:17:45PM +0200, Baruch Siach wrote:
> Hi Ressell,
> 
> On Wed, Feb 14, 2018 at 11:07:51AM +0000, Russell King - ARM Linux wrote:
> > On Wed, Feb 14, 2018 at 12:56:53PM +0200, Baruch Siach wrote:
> > > On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
> > > >  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> > > > 
> > > > > The CP110 component has 4 uart peripherals. All of them use the same clock
> > > > > gate for slow peripherals that is shared with the i2c and spi peripherals.
> > > > >
> > > > > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > > > 
> > > > Applied on mvebu/dt64
> > > 
> > > Thanks.
> > > 
> > > What about patch 2/2 in this series?
> > 
> > I'm not entirely convinced that it's something that should be done.
> > I know that some people are already using the UART headers for other
> > purposes (other than UART) and the later revision boards have the
> > placement of the microUSB fixed so it is accessible.
> > 
> > While you can tell Linux to use the other UART headers with this
> > patch, uboot won't use them, which means you can't configure the
> > boot loader without (in your case) taking the board out of the case.
> > 
> > I've a similar problem (with the mcbin in a rackmount case), and my
> > solution to that has been to put a single washer under the mounting
> > post near the microUSB to lift the board sufficiently to allow a
> > connector to be plugged in.  Sometimes simple hardware fixes are
> > better than software fixes.
> > 
> > Others have used a dremel to modify the case to access the microUSB.
> 
> Just for the record, I'm fine with dropping 'status = "okay"' from the mcbin 
> CP{0,1} UART nodes. This would still allow anyone who needs this functionality 
> to enable it with a simple .dts modification, or a run-time dtb modification 
> from the bootloader.

Talking more with Jon (who works for SolidRun, the board manufacturer),
the feeling there is:

1. Why enable both UART headers - it makes more sense (given your reason)
   to enable one as UART but keep the other as GPIO.  The labelling up of
   them being a UART is merely a historical artifact of the very early
   development of the board.

2. They are developer boards, not a final product.  Case modification is
   somewhat expected.

(2) is especially relevant when SFP support gets added - some of the
early revision boards have the SCL/SDA lines swapped on the I2C bus.
With that fixed, all boards have way too strong pull-ups on the I2C
bus which means some modules don't work - and worse than that, may
result in corrupted module EEPROMs.

I ended up with corruption here, and although I've a rev 1.3 board now,
I'm still using my self-modified rev 1.1 in preference to it, because
I don't want to have to deal with another corrupted EEPROM.

In order for SFP to be reliably functional, board modification is
required (either replacement of resistor packs, or in the case of the
early boards, cutting the I2C lines and rewiring them.)

IOW, board modification will be required for SFP on most mcbins.

-- 
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[PATCH v2 1/2] arm64: dts: marvell: add CP110 uart peripherals

[Gregory CLEMENT]

Hi,
 
 On mer., f?vr. 14 2018, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:

> On Wed, Feb 14, 2018 at 01:17:45PM +0200, Baruch Siach wrote:
>> Hi Ressell,
>> 
>> On Wed, Feb 14, 2018 at 11:07:51AM +0000, Russell King - ARM Linux wrote:
>> > On Wed, Feb 14, 2018 at 12:56:53PM +0200, Baruch Siach wrote:
>> > > On Wed, Feb 14, 2018 at 11:42:52AM +0100, Gregory CLEMENT wrote:
>> > > >  On mer., janv. 31 2018, Baruch Siach <baruch@tkos.co.il> wrote:
>> > > > 
>> > > > > The CP110 component has 4 uart peripherals. All of them use the same clock
>> > > > > gate for slow peripherals that is shared with the i2c and spi peripherals.
>> > > > >
>> > > > > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>> > > > 
>> > > > Applied on mvebu/dt64
>> > > 
>> > > Thanks.
>> > > 
>> > > What about patch 2/2 in this series?
>> > 
>> > I'm not entirely convinced that it's something that should be done.
>> > I know that some people are already using the UART headers for other
>> > purposes (other than UART) and the later revision boards have the
>> > placement of the microUSB fixed so it is accessible.
>> > 
>> > While you can tell Linux to use the other UART headers with this
>> > patch, uboot won't use them, which means you can't configure the
>> > boot loader without (in your case) taking the board out of the case.
>> > 
>> > I've a similar problem (with the mcbin in a rackmount case), and my
>> > solution to that has been to put a single washer under the mounting
>> > post near the microUSB to lift the board sufficiently to allow a
>> > connector to be plugged in.  Sometimes simple hardware fixes are
>> > better than software fixes.
>> > 
>> > Others have used a dremel to modify the case to access the microUSB.
>> 
>> Just for the record, I'm fine with dropping 'status = "okay"' from the mcbin 
>> CP{0,1} UART nodes. This would still allow anyone who needs this functionality 
>> to enable it with a simple .dts modification, or a run-time dtb modification 
>> from the bootloader.
>
> Talking more with Jon (who works for SolidRun, the board manufacturer),
> the feeling there is:
>
> 1. Why enable both UART headers - it makes more sense (given your reason)
>    to enable one as UART but keep the other as GPIO.  The labelling up of
>    them being a UART is merely a historical artifact of the very early
>    development of the board.
>
> 2. They are developer boards, not a final product.  Case modification is
>    somewhat expected.

Just to let know that I applied the patch but I still can either ammend
it or drop it as it is not yet part of an immutable tag.

Once you will have agreed I will do the change.

Gregory


>
> (2) is especially relevant when SFP support gets added - some of the
> early revision boards have the SCL/SDA lines swapped on the I2C bus.
> With that fixed, all boards have way too strong pull-ups on the I2C
> bus which means some modules don't work - and worse than that, may
> result in corrupted module EEPROMs.
>
> I ended up with corruption here, and although I've a rev 1.3 board now,
> I'm still using my self-modified rev 1.1 in preference to it, because
> I don't want to have to deal with another corrupted EEPROM.
>
> In order for SFP to be reliably functional, board modification is
> required (either replacement of resistor packs, or in the case of the
> early boards, cutting the I2C lines and rewiring them.)
>
> IOW, board modification will be required for SFP on most mcbins.
>
> -- 
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
> According to speedtest.net: 8.21Mbps down 510kbps up

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com