From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 213D7CA0EE4 for ; Mon, 18 Aug 2025 18:33:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Kn6jJsWi5SPOsaSWwVe4opV/tLtq4gsFhke9wUInT2w=; b=Xg5lyYny9Bc2R65BYCeeRPoPSH aiNHJNX59XYsVT+nuvVfmnBITMQ4BiYj9I23k0EfK10KhlS5OulLEqWr9cMKNcXbMu56sG9Zel3Fo xE9lnoVeMP1GFGqZapBgsViXwCFd05cbAvxQs4syfUHXDun5Tdo8rAXJNYX+0+kJa6XcHZwsjJcsE ZpooP2PUBb56ChRNiFFsDFZnv6rF+nXIAVVJv20MaDSRl+gQmXFx9WdfAoBNcbrwQp0EVOpFOetHy 2sh0CqKorMTDhjay2jiK+NTm1xsWU6/fGA7MwIVDiFrPyN/WQfi68Ud+yhlVNoKavy4l+loqDBMBH k6Lcy6uA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uo4fm-00000008Mr7-3a2R; Mon, 18 Aug 2025 18:33:34 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uo21F-00000007wYh-0YFB for linux-arm-kernel@lists.infradead.org; Mon, 18 Aug 2025 15:43:34 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 6460B418CD; Mon, 18 Aug 2025 15:43:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39E6FC4CEEB; Mon, 18 Aug 2025 15:43:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755531812; bh=2gw9bufPdvuGnWtKJzkTzSHcYSXunQ7KQaWLcstisag=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OdNd+gU2RzCHnheu7QHypV85qYdEmzkXGbMRwN4Ud74Gu7537V/ABBSmlTU32xpAW R+Y49WjaELw1uuf9aIRhtJ1LpMFcuNqTVDVIGWs/eU4iaX8tP7vlcSv8mTJIFjnVs5 M/+zJhzPrK05V/89tT/liw3X3Rr/PMVRpmU0lKchrSlqoQ01p+Ij0eF7WNMq0CNVrk iQ0t+WqUw42wFZ0JTwzDDPBPGWbcqH5vYCB/Dx7vKVFUjY9QkFRWtI60nzOpHf/f21 KIpf2zswgKLuI8VJqxBOqByd9GCOi33UgxPXKWj8tXZUlLvxxl3kbsar25O0XVgGFk 343glz0N3v44A== Received: from host86-149-246-145.range86-149.btcentralplus.com ([86.149.246.145] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uo218-008fTF-Hr; Mon, 18 Aug 2025 16:43:26 +0100 Date: Mon, 18 Aug 2025 16:43:06 +0100 Message-ID: <87ldngmy9h.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Oliver Upton , Mark Brown , Ryan Roberts , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] arm64/sysreg: Add TCR_EL2 register In-Reply-To: <20250818045759.672408-4-anshuman.khandual@arm.com> References: <20250818045759.672408-1-anshuman.khandual@arm.com> <20250818045759.672408-4-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 86.149.246.145 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, broonie@kernel.org, ryan.roberts@arm.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250818_084333_208445_D69F358D X-CRM114-Status: GOOD ( 22.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 18 Aug 2025 05:57:58 +0100, Anshuman Khandual wrote: > > Add TCR_EL2 register fields as per the latest ARM ARM DDI 0487 7.B in tools 7.B??? My copy of the published ARM ARM has L.B as the version suffix. Also, if you got the registers from the ARM ARM, please stop doing so. This is terribly error prone, and likely to be incomplete, given that the ARM ARM lags about a year behind the published architecture. You have the BSD-licensed MRS at your disposal, please make use of it. > sysreg format and drop all the existing redundant macros from the header > (arch/arm64/include/asm/kvm_arm.h). While here also drop an explicit sysreg > definction SYS_TCR_EL2 from sysreg.h header. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: Mark Brown > Cc: linux-arm-kernel@lists.infradead.org > Cc: kvmarm@lists.linux.dev > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/kvm_arm.h | 13 ---------- > arch/arm64/include/asm/sysreg.h | 1 - > arch/arm64/tools/sysreg | 44 ++++++++++++++++++++++++++++++++ > 3 files changed, 44 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 560d9cb63413..8994cddef182 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -107,19 +107,6 @@ > > #define MPAMHCR_HOST_FLAGS 0 > > -/* TCR_EL2 Registers bits */ > -#define TCR_EL2_DS (1UL << 32) > -#define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) > -#define TCR_EL2_HPD (1 << 24) > -#define TCR_EL2_TBI (1 << 20) > -#define TCR_EL2_PS_SHIFT 16 > -#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) > -#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) > -#define TCR_EL2_TG0_MASK TCR_EL1_TG0_MASK > -#define TCR_EL2_SH0_MASK TCR_EL1_SH0_MASK > -#define TCR_EL2_ORGN0_MASK TCR_EL1_ORGN0_MASK > -#define TCR_EL2_IRGN0_MASK TCR_EL1_IRGN0_MASK > -#define TCR_EL2_T0SZ_MASK 0x3f > #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ > TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ad5c901af229..112d5d0acb50 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -523,7 +523,6 @@ > > #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) > #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) > -#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) > #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 4bdae8bb11dc..d2b40105eb41 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -4812,6 +4812,50 @@ Sysreg TCR_EL12 3 5 2 0 2 > Mapping TCR_EL1 > EndSysreg > > +Sysreg TCR_EL2 3 4 2 0 2 > +Res0 63:34 > +Field 33 MTX > +Field 32 DS > +Res1 31 > +Field 30 TCMA > +Field 29 TBID > +Field 28 HWU62 > +Field 27 HWU61 > +Field 26 HWU60 > +Field 25 HWU59 > +Field 24 HPD > +Res1 23 > +Field 22 HD > +Field 21 HA > +Field 20 TBI > +Res0 19 > +Field 18:16 PS > +UnsignedEnum 15:14 TG0 > + 0b00 4K > + 0b01 64K > + 0b10 16K > +EndEnum > +UnsignedEnum 13:12 SH0 > + 0b00 NONE > + 0b10 OUTER > + 0b11 INNER > +EndEnum > +UnsignedEnum 11:10 ORGN0 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > +UnsignedEnum 9:8 IRGN0 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > +Res0 7:6 > +Field 5:0 T0SZ > +EndSysreg This is only the E2H==0 version of TCR_EL2. IF you are going to describe this register in a useful manner, then add both formats so that we know what we are dealing with. M. -- Jazz isn't dead. It just smells funny.