Re: [PATCH 1/2] KVM: arm64: nvhe: Synchronise with page table walker on MMU update

From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>
Subject: Re: [PATCH 1/2] KVM: arm64: nvhe: Synchronise with page table walker on MMU update
Date: Fri, 07 Apr 2023 12:37:11 +0100	[thread overview]
Message-ID: <87lej36hzs.wl-maz@kernel.org> (raw)
In-Reply-To: <87mt3k53x9.wl-maz@kernel.org>

On Fri, 07 Apr 2023 12:26:26 +0100,
Marc Zyngier <maz@kernel.org> wrote:
> 
> Hi Oliver,
> 
> On Thu, 06 Apr 2023 17:56:31 +0100,
> Oliver Upton <oliver.upton@linux.dev> wrote:
> > 
> > Hey Marc,
> > 
> > On Thu, Mar 30, 2023 at 11:04:18AM +0100, Marc Zyngier wrote:
> > > When taking an exception between the EL1&0 translation regime and
> > > the EL2 translation regime, the page table walker is allowed to
> > > complete the walks started from EL0 or EL1 while running at EL2.
> > > 
> > > It means that altering the system registers that define the EL1&0
> > > translation regime is fraught with danger *unless* we wait for
> > > the completion of such walk with a DSB (R_LFHQG and subsequent
> > > statements in the ARM ARM). We already did the right thing for
> > > other external agents (SPE, TRBE), but not the PTW.
> > > 
> > > In the case of nVHE, this is a bit involved, as there are a number
> > > of situations where this can happen (such as switching between
> > > host and guest, invalidating TLBs...).
> > 
> > I'm assuming that the dsb(ishst) done in some of the other TLB
> > invalidation handlers is sufficient, as R_LFHQG does not describe the
> > scope of the DSB (i.e. loads and/or stores). Nonetheless, short of any
> > special serialization rules, it seems probable for the PTW to have both
> > outstanding loads and stores.
> 
> I too find the definition pretty light. My gut feeling is that we're
> not really trying to synchronise against either loads or stores. We
> are simply waiting for the PTW to complete (or give up) potential
> speculative walks.
> 
> For TLBIs, we want to make sure that prior writes to the PTs are
> observable, specially as we perform a broadcast invalidation.
> 
> But for external agents, we seem to always rely on an dsb(nsh), such
> as for TRBE and SPE. My take is that if it is enough for them, it
> should be enough for the PTW.

I'll also add that dsb(nsh) orders both reads and writes either side
of the barrier.

However, I finally get your point about the TLBI code. It only orders
stores either side of the barrier, and I'm starting to wonder whether
we should upgrade it to dsb(ish)...

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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