From: Marc Zyngier <maz@kernel.org>
To: "Pali Rohár" <pali@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
kernel-team@android.com, Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] PCI: apple: Reset the port for 100ms on probe
Date: Thu, 18 Nov 2021 10:45:04 +0000 [thread overview]
Message-ID: <87lf1l7nf3.wl-maz@kernel.org> (raw)
In-Reply-To: <87o86h7pex.wl-maz@kernel.org>
On Thu, 18 Nov 2021 10:01:58 +0000,
Marc Zyngier <maz@kernel.org> wrote:
>
> There is also a third delay (Tperst-clk) which represents the time
> required for the clock to ramp up before releasing #PERST. No, there
> is no value associated with this.
Actually, there is. At least the PCIe CMS r2.0 (2.6.2. AC
Specifications) does provide a table of the timings. Tperst-clk has a
minimum value of 100us.
Which means I can tighten things further.
M.
--
Without deviation from the norm, progress is not possible.
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prev parent reply other threads:[~2021-11-18 10:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-17 16:00 [PATCH] PCI: apple: Reset the port for 100ms on probe Marc Zyngier
2021-11-17 20:12 ` Bjorn Helgaas
2021-11-17 20:28 ` Pali Rohár
2021-11-18 10:01 ` Marc Zyngier
2021-11-18 10:31 ` Pali Rohár
2021-11-18 12:57 ` Marc Zyngier
2021-11-20 11:32 ` Pali Rohár
2021-11-18 10:45 ` Marc Zyngier [this message]
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