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Thu, 15 Jul 2021 12:26:32 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m40QU-000mj2-NP for linux-arm-kernel@lists.infradead.org; Thu, 15 Jul 2021 12:25:16 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 66E5F611AB; Thu, 15 Jul 2021 12:25:14 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m40QS-00DWYJ-Ae; Thu, 15 Jul 2021 13:25:12 +0100 Date: Thu, 15 Jul 2021 13:25:11 +0100 Message-ID: <87lf67kbmg.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Cc: Alexandru Elisei , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Alexandre Chartre , kernel-team@android.com Subject: Re: [PATCH 1/3] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements In-Reply-To: References: <20210713135900.1473057-1-maz@kernel.org> <20210713135900.1473057-2-maz@kernel.org> <87mtqnkf1w.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, alexandre.chartre@oracle.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210715_052514_837554_10D37EEF X-CRM114-Status: GOOD ( 37.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 15 Jul 2021 12:51:49 +0100, Robin Murphy wrote: > > On 2021-07-15 12:11, Marc Zyngier wrote: > > Hi Alex, > > > > On Wed, 14 Jul 2021 16:48:07 +0100, > > Alexandru Elisei wrote: > >> > >> Hi Marc, > >> > >> On 7/13/21 2:58 PM, Marc Zyngier wrote: > >>> A number of the PMU sysregs expose reset values that are not in > >>> compliant with the architecture (set bits in the RES0 ranges, > >>> for example). > >>> > >>> This in turn has the effect that we need to pointlessly mask > >>> some register when using them. > >>> > >>> Let's start by making sure we don't have illegal values in the > >>> shadow registers at reset time. This affects all the registers > >>> that dedicate one bit per counter, the counters themselves, > >>> PMEVTYPERn_EL0 and PMSELR_EL0. > >>> > >>> Reported-by: Alexandre Chartre > >>> Signed-off-by: Marc Zyngier > >>> --- > >>> arch/arm64/kvm/sys_regs.c | 46 ++++++++++++++++++++++++++++++++++++--- > >>> 1 file changed, 43 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > >>> index f6f126eb6ac1..95ccb8f45409 100644 > >>> --- a/arch/arm64/kvm/sys_regs.c > >>> +++ b/arch/arm64/kvm/sys_regs.c > >>> @@ -603,6 +603,44 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, > >>> return REG_HIDDEN; > >>> } > >>> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct > >>> sys_reg_desc *r) > >>> +{ > >>> + u64 n, mask; > >>> + > >>> + /* No PMU available, any PMU reg may UNDEF... */ > >>> + if (!kvm_arm_support_pmu_v3()) > >>> + return; > >>> + > >>> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; > >> > >> Isn't this going to cause a lot of unnecessary traps with NV? Is > >> that going to be a problem? > > > > We'll get a new traps at L2 VM creation if we expose a PMU to the L1 > > guest, and if L2 gets one too. I don't think that's a real problem, as > > the performance of an L2 PMU is bound to be hilarious, and if we are > > really worried about that, we can always cache it locally. Which is > > likely the best thing to do if you think of big-little. > > > > Let's not think of big-little. > > > > Another thing is that we could perfectly ignore the number of counter > > on the host and always expose the architectural maximum, given that > > the PMU is completely emulated. With that, no trap. > > Although that would deliberately exacerbate the existing problem of > guest counters mysteriously under-reporting due to the host event > getting multiplexed, thus arguably make the L2 PMU even less useful. Oh, absolutely. But the current implementation of the PMU emulation would be pretty terrible on NV anyway. > But then trying to analyse application performance under NV at all > seems to stand a high chance of being akin to shovelling fog, so... Indeed. Not to mention that there is no (publicly available) HW to measure performance on anyway... M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel