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Fri, 29 May 2020 07:04:25 -0700 References: <20200513125532.24585-1-lars.povlsen@microchip.com> <20200513125532.24585-11-lars.povlsen@microchip.com> <159054759981.88029.2630901114208720574@swboyd.mtv.corp.google.com> From: Lars Povlsen To: Stephen Boyd Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock In-Reply-To: <159054759981.88029.2630901114208720574@swboyd.mtv.corp.google.com> Date: Fri, 29 May 2020 16:04:32 +0200 Message-ID: <87lflaq1lb.fsf@soft-dev15.microsemi.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200529_070449_289086_BECA0B00 X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: devicetree@vger.kernel.org, Alexandre Belloni , Arnd Bergmann , linux-gpio@vger.kernel.org, Steen Hegelund , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support , Michael Turquette , SoC Team , Rob Herring , linux-arm-kernel@lists.infradead.org, Olof Johansson , Linus Walleij , Lars Povlsen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Stephen Boyd writes: > Quoting Lars Povlsen (2020-05-13 05:55:28) >> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml >> new file mode 100644 >> index 0000000000000..594007d8fc59a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml >> @@ -0,0 +1,46 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip Sparx5 DPLL Clock >> + >> +maintainers: >> + - Lars Povlsen >> + >> +description: | >> + The Sparx5 DPLL clock controller generates and supplies clock to >> + various peripherals within the SoC. >> + >> + This binding uses common clock bindings >> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt > > I don't think we need this sentence. Please drop it. OK. (Assuming the "This binding ..." part). > >> + >> +properties: >> + compatible: >> + const: microchip,sparx5-dpll >> + >> + reg: >> + items: >> + - description: dpll registers >> + >> + '#clock-cells': >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - '#clock-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + # Clock provider for eMMC: >> + - | >> + clks: clks@61110000c { > > Node name should be clock-controller@61110000c Ok. > >> + compatible = "microchip,sparx5-dpll"; >> + #clock-cells = <1>; >> + reg = <0x1110000c 0x24>; > > Does it consume any clks itself? I'd expect to see some sort of 'clocks' > property in this node. > >> + }; I changed the driver to use a fixed-rate input clock, replacing the BASE_CLOCK define(s). Additionally, I made the ahb_clock into fixed-factor clock using the A53 cpu clock as a base. So I updated the example and added 'clocks' to the schema. I will send you a new series shortly. Thank you for the comments. -- Lars Povlsen, Microchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel