From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0973C3DA49 for ; Sun, 28 Jul 2024 21:56:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Message-ID:Date:References:In-Reply-To:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZtA4t5LZ40hEoX4e5ac+/ORpoeeCKNJbbgE1EAlkPdM=; b=xfQNT3eqlj68PBBP4cFnApPReM /XZ1kx49LCFHo2FNfs/VMP/bIC3v0sd3rQe2foCC3kybhrDkK5GgOm7iw/Y2+M1mgv/r5333K97SA xHtukR67E8OicjUahdpzKiCdiLy7yknYNSi+xSzhrfENwyWhfhEdlW+MMtkwHTO3CMnep2AmXt7fB NwP/riCZ0K0EJqXOKmCduV0gJX2L7hVwPRlCA/+fmQxWkR9SB0DAt0febPWPx6OdVuDdiczfy2RIB yByTKyEM77MkGEBiCARnpFm8CgL4tzs9cwtLUtz8VwMOriPz5zxkhtYp2ARVTq1ihkMMeGc1ZSZbt iceFqjzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYBsR-00000009Ist-0IJA; Sun, 28 Jul 2024 21:56:27 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYBry-00000009IqR-2ZMz for linux-arm-kernel@lists.infradead.org; Sun, 28 Jul 2024 21:56:02 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722203757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZtA4t5LZ40hEoX4e5ac+/ORpoeeCKNJbbgE1EAlkPdM=; b=T7A1OJMNJayvOy1N4nn/hu5cG6IMm9NaVwDUwwZHfQ/6nK3qRlTXgYtfN3LBBI/fLaL1+p zFAu7sGin8KWf+j1Kkr0m1iNlmg8wfKl68JOlgt4x6ZKafHdXQDYClxCO4R/e7mFyohU33 RHRUdgmYrPvHmVCZ8jBr5A4bd3wcRBH2bsL5Gfrcua6Et/yuRGWbjtHW3qkVDga0mK4kA/ F3PgVIMf9Kr+kye0x/b6oUvIcsosV8Q3eUkBFI3Q5C45eD+ALFIoMkga0+TgWqm1x4uOl9 IOiX1nIp/gJ9mbNzQiuR1mavXtLZqwKCS61wXkU6r5jXPHjNfWqKMAqqKR/ZAQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722203757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZtA4t5LZ40hEoX4e5ac+/ORpoeeCKNJbbgE1EAlkPdM=; b=z6z2xqeZQ0hg5YDpO/su4EId6QiwRma7xRyKc1x+rMhHk5iu1a/Jc4JZfmGzS6aIEIIksu Zki+KQ7FiQBW9MCQ== To: Marek =?utf-8?Q?Beh=C3=BAn?= , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , Ilpo =?utf-8?Q?J=C3=A4rvinen?= Cc: Marek =?utf-8?Q?Beh=C3=BAn?= Subject: Re: [PATCH 12/13] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts In-Reply-To: <20240715105156.18388-13-kabel@kernel.org> References: <20240715105156.18388-1-kabel@kernel.org> <20240715105156.18388-13-kabel@kernel.org> Date: Sun, 28 Jul 2024 23:55:56 +0200 Message-ID: <87msm1rxjn.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_145558_817093_317F5565 X-CRM114-Status: UNSURE ( 6.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 15 2024 at 12:51, Marek Beh=C3=BAn wrote: > On platforms where MPIC is not the top-level interrupt controller the > driver currently only supports handling of the per-CPU interrupts (the > first 29 interrupts). This is obvious from the code of > mpic_handle_cascade_irq(), where we read only one cause register. which reads only .... We read nothing :) Thanks, tglx