From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7FAFEC433EF for ; Fri, 25 Feb 2022 14:40:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ycmOszMbRRPQGqVUJECeQ/RlgtpgIj8MRAI95oqlq1s=; b=gD5H6px+UkL6iq Wn8m3KgqaXXqcJ7RxoeGQsTuLuYBYZiP+WC18ijn3BIZzvnMlYOI2h27dqCOfvhNW9cVInYnUPLH8 29kKPdQe37LkoVXX44iHgf2F/NuyYVW+4RFXqJBHZxljRKHUq5wRGIgKi4O7N+hsQU3GyQ5t/Hryz kUOxJ2a0a1YREyHntoGNZ4/s3soRFqD3N1rUMU1lL5vm0j7/crVdUzG/aQeVz3uwFxM8D4t77NDSR mrhLV41KvOa3Z/TmXHYKG7FSqp6DvNALM2C9ksZNSH8emUzNAd7LgHhImfGjXOOYG+KDirQVvjMFa Pb6+s0xjgFqBRo2wk8FA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNbkr-005Qq4-6d; Fri, 25 Feb 2022 14:39:33 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNbkm-005QpR-Hj for linux-arm-kernel@lists.infradead.org; Fri, 25 Feb 2022 14:39:30 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 17574612B5; Fri, 25 Feb 2022 14:39:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5AEAEC340E7; Fri, 25 Feb 2022 14:39:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645799967; bh=cNgfaXX/ZY2ofKk0wyVNQWz4wXK1w3ilqbl4W9JFkyQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=dvMXNfEp5LbXneNtmXndDp6B4ROeUk4WyLcH3nwf6ImqOwMzQvlPqEFJM2qEUSiSn gVh/AmdWq7Cqr5hGjd8II945ud7TiUXtTqSnIQjesKin91DmTgISJTs+NV05TiaWLY RNJOmY0uuhTa938PoQnNxCQlOews8NGtk5V3dElPnYvNMvdUKgJD3SGOW3wZ6rn3On w8+HeRrHlfLy3e1+a9SR4S9hi0ipxh6ZYRzgeRFD+IxshliLFDdICby0cUIvr1CN7G l44qdugBtMNxITvpEIu0sD/Ctm+EUk6xGPvbUuzrrCVoDrgs/TL7YqNn1DM0jhrbCA TeCSBXkgWSb3A== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nNbkj-00AYAh-6t; Fri, 25 Feb 2022 14:39:25 +0000 Date: Fri, 25 Feb 2022 14:39:24 +0000 Message-ID: <87mtif2eoz.wl-maz@kernel.org> From: Marc Zyngier To: Hector Martin Cc: Thomas Gleixner , Rob Herring , Sven Peter , Alyssa Rosenzweig , Mark Kettenis , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support In-Reply-To: <20220224130741.63924-4-marcan@marcan.st> References: <20220224130741.63924-1-marcan@marcan.st> <20220224130741.63924-4-marcan@marcan.st> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: marcan@marcan.st, tglx@linutronix.de, robh+dt@kernel.org, sven@svenpeter.dev, alyssa@rosenzweig.io, mark.kettenis@xs4all.nl, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220225_063928_694207_8CA63399 X-CRM114-Status: GOOD ( 39.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 24 Feb 2022 13:07:37 +0000, Hector Martin wrote: > > The newer AICv2 present in t600x SoCs does not have legacy IPI support > at all. Since t8103 also supports Fast IPIs, implement support for this > first. The legacy IPI code is left as a fallback, so it can be > potentially used by older SoCs in the future. > > The vIPI code is shared; only the IPI firing/acking bits change for Fast > IPIs. > > Signed-off-by: Hector Martin > --- > drivers/irqchip/irq-apple-aic.c | 122 ++++++++++++++++++++++++++++---- > 1 file changed, 109 insertions(+), 13 deletions(-) > > diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c > index 38091ebb9403..613e0ebdabdc 100644 > --- a/drivers/irqchip/irq-apple-aic.c > +++ b/drivers/irqchip/irq-apple-aic.c > @@ -24,7 +24,7 @@ > * - Default "this CPU" register view and explicit per-CPU views > * > * In addition, this driver also handles FIQs, as these are routed to the same > - * IRQ vector. These are used for Fast IPIs (TODO), the ARMv8 timer IRQs, and > + * IRQ vector. These are used for Fast IPIs, the ARMv8 timer IRQs, and > * performance counters (TODO). > * > * Implementation notes: > @@ -52,9 +52,11 @@ > #include > #include > #include > +#include > #include > #include > #include > +#include > #include > #include > #include > @@ -106,7 +108,6 @@ > > /* > * IMP-DEF sysregs that control FIQ sources > - * Note: sysreg-based IPIs are not supported yet. > */ > > /* Core PMC control register */ > @@ -155,6 +156,10 @@ > #define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4) > #define UPMSR_IACT BIT(0) > > +/* MPIDR fields */ > +#define MPIDR_CPU(x) MPIDR_AFFINITY_LEVEL(x, 0) > +#define MPIDR_CLUSTER(x) MPIDR_AFFINITY_LEVEL(x, 1) > + > #define AIC_NR_FIQ 4 > #define AIC_NR_SWIPI 32 > > @@ -173,11 +178,44 @@ > #define AIC_TMR_EL02_PHYS AIC_TMR_GUEST_PHYS > #define AIC_TMR_EL02_VIRT AIC_TMR_GUEST_VIRT > > +DEFINE_STATIC_KEY_TRUE(use_fast_ipi); > + > +struct aic_info { > + int version; > + > + /* Features */ > + bool fast_ipi; > +}; > + > +static const struct aic_info aic1_info = { > + .version = 1, > +}; > + > +static const struct aic_info aic1_fipi_info = { > + .version = 1, > + > + .fast_ipi = true, > +}; > + > +static const struct of_device_id aic_info_match[] = { > + { > + .compatible = "apple,t8103-aic", > + .data = &aic1_fipi_info, > + }, > + { > + .compatible = "apple,aic", > + .data = &aic1_info, > + }, > + {} > +}; > + > struct aic_irq_chip { > void __iomem *base; > struct irq_domain *hw_domain; > struct irq_domain *ipi_domain; > int nr_hw; > + > + struct aic_info info; > }; > > static DEFINE_PER_CPU(uint32_t, aic_fiq_unmasked); > @@ -386,8 +424,12 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs) > */ > > if (read_sysreg_s(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING) { > - pr_err_ratelimited("Fast IPI fired. Acking.\n"); > - write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); > + if (static_branch_likely(&use_fast_ipi)) { > + aic_handle_ipi(regs); > + } else { > + pr_err_ratelimited("Fast IPI fired. Acking.\n"); > + write_sysreg_s(IPI_SR_PENDING, SYS_IMP_APL_IPI_SR_EL1); > + } > } > > if (TIMER_FIRING(read_sysreg(cntp_ctl_el0))) > @@ -563,6 +605,22 @@ static const struct irq_domain_ops aic_irq_domain_ops = { > * IPI irqchip > */ > > +static void aic_ipi_send_fast(int cpu) > +{ > + u64 mpidr = cpu_logical_map(cpu); > + u64 my_mpidr = read_cpuid_mpidr(); > + u64 cluster = MPIDR_CLUSTER(mpidr); > + u64 idx = MPIDR_CPU(mpidr); > + > + if (MPIDR_CLUSTER(my_mpidr) == cluster) > + write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), > + SYS_IMP_APL_IPI_RR_LOCAL_EL1); > + else > + write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx) | FIELD_PREP(IPI_RR_CLUSTER, cluster), > + SYS_IMP_APL_IPI_RR_GLOBAL_EL1); > + isb(); I think you have an ordering issue with this, see below. > +} > + > static void aic_ipi_mask(struct irq_data *d) > { > u32 irq_bit = BIT(irqd_to_hwirq(d)); > @@ -588,8 +646,12 @@ static void aic_ipi_unmask(struct irq_data *d) > * If a pending vIPI was unmasked, raise a HW IPI to ourselves. > * No barriers needed here since this is a self-IPI. > */ > - if (atomic_read(this_cpu_ptr(&aic_vipi_flag)) & irq_bit) > - aic_ic_write(ic, AIC_IPI_SEND, AIC_IPI_SEND_CPU(smp_processor_id())); > + if (atomic_read(this_cpu_ptr(&aic_vipi_flag)) & irq_bit) { > + if (static_branch_likely(&use_fast_ipi)) > + aic_ipi_send_fast(smp_processor_id()); > + else > + aic_ic_write(ic, AIC_IPI_SEND, AIC_IPI_SEND_CPU(smp_processor_id())); > + } > } > > static void aic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) > @@ -617,8 +679,12 @@ static void aic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) > smp_mb__after_atomic(); > > if (!(pending & irq_bit) && > - (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) > - send |= AIC_IPI_SEND_CPU(cpu); > + (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) { > + if (static_branch_likely(&use_fast_ipi)) > + aic_ipi_send_fast(cpu); OK, this is suffering from the same issue that GICv3 has, which is that memory barriers don't provide order against sysregs. You need a DSB for that, which is a pain. Something like this: diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c index 602c8b274170..579f22b72339 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -736,6 +736,15 @@ static void aic_ipi_send_fast(int cpu) u64 cluster = MPIDR_CLUSTER(mpidr); u64 idx = MPIDR_CPU(mpidr); + /* + * A DSB is required here in to order prior writes to memory + * with system register accesses having a side effect + * (matching the behaviour of the IPI registers). Make sure we + * only order stores with in the IS domain, keeping as light + * as possible. + */ + dsb(ishst); + if (MPIDR_CLUSTER(my_mpidr) == cluster) write_sysreg_s(FIELD_PREP(IPI_RR_CPU, idx), SYS_IMP_APL_IPI_RR_LOCAL_EL1); Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel