From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD562C4338F for ; Sun, 8 Aug 2021 10:31:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A067260551 for ; Sun, 8 Aug 2021 10:31:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A067260551 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ssxfjyrQqrwLUHID+nRgepUm5/+uDYdMXfQ9T0W5w80=; b=wKbaItt2usykCm JNBwTxnIPSslklHEsKgBa/m7wWL2KHPeWJaaNzAKysa7kK+zr4fkkbR8ba/jvaZzU6No8T6mhA1KI 7h54lWCM4MlUqURN8dkbOwHKmDcfG4ZOZRbL/yHFXZHPtRWvgMy2yagRA+UBeM2tEAz275c1HT/n3 zMln4RuY1Bw2Czspk/+ZRVbySsoyqGgtbMOzmS7/IZJfimENagzkq8G1aKQT3vGcMFwPCxDOOES80 YJBm5DxFYcGn4JbWjoWJt9YWkFlCZfkqMyYIj3JEpJJC8qy/vk8RaUCxhZFDp4R3wvWs31mLa4tuN At4O7oA2F/wkAfq2kwKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mCg47-00FjDq-Jy; Sun, 08 Aug 2021 10:29:59 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mCg43-00FjDT-HA for linux-arm-kernel@lists.infradead.org; Sun, 08 Aug 2021 10:29:56 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F0BA461002; Sun, 8 Aug 2021 10:29:54 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mCg40-003cNF-VI; Sun, 08 Aug 2021 11:29:53 +0100 Date: Sun, 08 Aug 2021 11:29:52 +0100 Message-ID: <87mtps1b6n.wl-maz@kernel.org> From: Marc Zyngier To: Linus Walleij Cc: Oliver Upton , Linux ARM , linux-kernel , Mark Rutland , Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller Subject: Re: [PATCH v2] clocksource/arm_arch_timer: Fix masking for high freq counters In-Reply-To: References: <20210807191428.3488948-1-oupton@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linus.walleij@linaro.org, oupton@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, pshier@google.com, rananta@google.com, ricarkol@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210808_032955_634128_3FD3FEAF X-CRM114-Status: GOOD ( 30.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 07 Aug 2021 23:30:20 +0100, Linus Walleij wrote: > > On Sat, Aug 7, 2021 at 9:14 PM Oliver Upton wrote: > > > Unfortunately, the architecture provides no means to determine the bit > > width of the system counter. However, we do know the following from the > > specification: > > > > - the system counter is at least 56 bits wide > > - Roll-over time of not less than 40 years > > > > To date, the arch timer driver has depended on the first property, > > assuming any system counter to be 56 bits wide and masking off the rest. > > However, combining a narrow clocksource mask with a high frequency > > counter could result in prematurely wrapping the system counter by a > > significant margin. For example, a 56 bit wide, 1GHz system counter > > would wrap in a mere 2.28 years! > > > > This is a problem for two reasons: v8.6+ implementations are required to > > provide a 64 bit, 1GHz system counter. Furthermore, before v8.6, > > implementers may select a counter frequency of their choosing. > > > > Fix the issue by deriving a valid clock mask based on the second > > property from above. Set the floor at 56 bits, since we know no system > > counter is narrower than that. > > > > Suggested-by: Marc Zyngier > > Signed-off-by: Oliver Upton > > This patch looks good to me: > Reviewed-by: Linus Walleij > > Just a thought that crossed my mind: as this is real hardware we are > talking about mostly, how hard would it be for arch_counter_get_width() > to detect how wide it actually is if nbits > 56? > > I would do something like this pseudocode: > > nbits = 56; > while (nbits < 64) > startval = GENMASK(nbits, 0); > write_counter(startval); That's where things stop. The counter is not writable, and for good reasons (it is shared with all the CPUs in the system). > start_counter; > nsleep(1); > stop_counter; > now = read_counter; > if (now < startval) > /* Ooops it wrapped */ > break; > nbits++ > > pr_info("counter has %d bits\n", nbits); > > Or did you folks already try this approach? The only way to emulate this behaviour is to use CNTVOFF_EL2 at EL2 to offset a guest view of the counter, and to run minimal guest that will do the start/stop/compare work. Given that it involves running a guest at a point where we are unable to do so, and that it cannot work when booted at EL1, we're left with guesswork. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel