[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Gregory CLEMENT]

The Armada 7K/8K SoCs use the same RTC IP than the Armada 38x. However
the SOC integration differs in 2 points:
     - MBUS bridge timing initialization
     - IRQ configuration at SoC level

This patch set extends the driver support to these SoCs family.

In this second version the device tree was updated allowing to use the
RTC on Armada 80x0 SoCs. Indeed on the Armada 80x0, the RTC clock in
CP master is not connected (by package) to the oscillator. So this one
is disabled for the Armada 8020 and the Armada 8040. On these SoCs it
will be the RTC clock in CP slave connected to the oscillator which
will be used.

Thanks,

Gregory

Gregory CLEMENT (3):
  rtc: armada38x: Prepare driver to manage different versions
  rtc: armada38x: Add support for Armada 7K/8K
  arm64: dts: marvell: add RTC description for Armada 7K/8K

 .../devicetree/bindings/rtc/armada-380-rtc.txt     |   8 +-
 arch/arm64/boot/dts/marvell/armada-8020.dtsi       |  10 +
 arch/arm64/boot/dts/marvell/armada-8040.dtsi       |   9 +
 .../boot/dts/marvell/armada-cp110-master.dtsi      |   7 +
 .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |   7 +
 drivers/rtc/rtc-armada38x.c                        | 217 ++++++++++++++++-----
 6 files changed, 202 insertions(+), 56 deletions(-)

-- 
2.11.0

[PATCH v2 1/3] rtc: armada38x: Prepare driver to manage different versions

[Gregory CLEMENT]

In order to prepare the introduction of the A7K/A8K version of the RTC,
this commit introduces a new data structure. This structure allows to
handle the differences between the integration of the RTC IP in the
SoCs. It will be:
 - MBUS bridge timing initialization
 - IRQ configuration at SoC level

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/rtc/rtc-armada38x.c | 152 +++++++++++++++++++++++++++++---------------
 1 file changed, 99 insertions(+), 53 deletions(-)

diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c
index 7cb5b27189db..b2a8e2ed71ca 100644
--- a/drivers/rtc/rtc-armada38x.c
+++ b/drivers/rtc/rtc-armada38x.c
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/rtc.h>
 
@@ -23,23 +24,23 @@
 #define RTC_STATUS_ALARM1	    BIT(0)
 #define RTC_STATUS_ALARM2	    BIT(1)
 #define RTC_IRQ1_CONF	    0x4
-#define RTC_IRQ1_AL_EN		    BIT(0)
-#define RTC_IRQ1_FREQ_EN	    BIT(1)
-#define RTC_IRQ1_FREQ_1HZ	    BIT(2)
+#define RTC_IRQ_AL_EN		    BIT(0)
+#define RTC_IRQ_FREQ_EN		    BIT(1)
+#define RTC_IRQ_FREQ_1HZ	    BIT(2)
+
 #define RTC_TIME	    0xC
 #define RTC_ALARM1	    0x10
-
-#define SOC_RTC_BRIDGE_TIMING_CTL   0x0
-#define SOC_RTC_PERIOD_OFFS		0
-#define SOC_RTC_PERIOD_MASK		(0x3FF << SOC_RTC_PERIOD_OFFS)
-#define SOC_RTC_READ_DELAY_OFFS		26
-#define SOC_RTC_READ_DELAY_MASK		(0x1F << SOC_RTC_READ_DELAY_OFFS)
-
-#define SOC_RTC_INTERRUPT   0x8
-#define SOC_RTC_ALARM1		BIT(0)
-#define SOC_RTC_ALARM2		BIT(1)
-#define SOC_RTC_ALARM1_MASK	BIT(2)
-#define SOC_RTC_ALARM2_MASK	BIT(3)
+#define RTC_38X_BRIDGE_TIMING_CTL   0x0
+#define RTC_38X_PERIOD_OFFS		0
+#define RTC_38X_PERIOD_MASK		(0x3FF << RTC_38X_PERIOD_OFFS)
+#define RTC_38X_READ_DELAY_OFFS		26
+#define RTC_38X_READ_DELAY_MASK		(0x1F << RTC_38X_READ_DELAY_OFFS)
+
+#define SOC_RTC_INTERRUPT	    0x8
+#define SOC_RTC_ALARM1			BIT(0)
+#define SOC_RTC_ALARM2			BIT(1)
+#define SOC_RTC_ALARM1_MASK		BIT(2)
+#define SOC_RTC_ALARM2_MASK		BIT(3)
 
 #define SAMPLE_NR 100
 
@@ -55,6 +56,19 @@ struct armada38x_rtc {
 	spinlock_t	    lock;
 	int		    irq;
 	struct value_to_freq *val_to_freq;
+	struct armada38x_rtc_data *data;
+};
+
+#define ALARM1	0
+#define ALARM_REG(base, alarm)	 ((base) + (alarm) * sizeof(u32))
+
+struct armada38x_rtc_data {
+	/* Initialize the RTC-MBUS bridge timing */
+	void (*update_mbus_timing)(struct armada38x_rtc *rtc);
+	u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
+	void (*clear_isr)(struct armada38x_rtc *rtc);
+	void (*unmask_interrupt)(struct armada38x_rtc *rtc);
+	u32 alarm;
 };
 
 /*
@@ -76,19 +90,19 @@ static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
 }
 
 /* Update RTC-MBUS bridge timing parameters */
-static void rtc_update_mbus_timing_params(struct armada38x_rtc *rtc)
+static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
 {
 	u32 reg;
 
-	reg = readl(rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);
-	reg &= ~SOC_RTC_PERIOD_MASK;
-	reg |= 0x3FF << SOC_RTC_PERIOD_OFFS; /* Maximum value */
-	reg &= ~SOC_RTC_READ_DELAY_MASK;
-	reg |= 0x1F << SOC_RTC_READ_DELAY_OFFS; /* Maximum value */
-	writel(reg, rtc->regs_soc + SOC_RTC_BRIDGE_TIMING_CTL);
+	reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
+	reg &= ~RTC_38X_PERIOD_MASK;
+	reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
+	reg &= ~RTC_38X_READ_DELAY_MASK;
+	reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
+	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
 }
 
-static u32 read_rtc_register_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
+static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
 {
 	int i, index_max = 0, max = 0;
 
@@ -130,13 +144,26 @@ static u32 read_rtc_register_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
 	return rtc->val_to_freq[index_max].value;
 }
 
+static void armada38x_clear_isr(struct armada38x_rtc *rtc)
+{
+	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
+
+	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
+}
+
+static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
+{
+	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
+
+	writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
+}
 static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
 {
 	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
 	unsigned long time, flags;
 
 	spin_lock_irqsave(&rtc->lock, flags);
-	time = read_rtc_register_wa(rtc, RTC_TIME);
+	time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
 	spin_unlock_irqrestore(&rtc->lock, flags);
 
 	rtc_time_to_tm(time, tm);
@@ -167,12 +194,14 @@ static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 {
 	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
 	unsigned long time, flags;
+	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
+	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
 	u32 val;
 
 	spin_lock_irqsave(&rtc->lock, flags);
 
-	time = read_rtc_register_wa(rtc, RTC_ALARM1);
-	val = read_rtc_register_wa(rtc, RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN;
+	time = rtc->data->read_rtc_reg(rtc, reg);
+	val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
 
 	spin_unlock_irqrestore(&rtc->lock, flags);
 
@@ -185,9 +214,10 @@ static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 {
 	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
+	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
+	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
 	unsigned long time, flags;
 	int ret = 0;
-	u32 val;
 
 	ret = rtc_tm_to_time(&alrm->time, &time);
 
@@ -196,13 +226,11 @@ static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 
 	spin_lock_irqsave(&rtc->lock, flags);
 
-	rtc_delayed_write(time, rtc, RTC_ALARM1);
+	rtc_delayed_write(time, rtc, reg);
 
 	if (alrm->enabled) {
-			rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
-			val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
-			writel(val | SOC_RTC_ALARM1_MASK,
-			       rtc->regs_soc + SOC_RTC_INTERRUPT);
+		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
+		rtc->data->unmask_interrupt(rtc);
 	}
 
 	spin_unlock_irqrestore(&rtc->lock, flags);
@@ -215,14 +243,15 @@ static int armada38x_rtc_alarm_irq_enable(struct device *dev,
 					 unsigned int enabled)
 {
 	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
+	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
 	unsigned long flags;
 
 	spin_lock_irqsave(&rtc->lock, flags);
 
 	if (enabled)
-		rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
+		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
 	else
-		rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
+		rtc_delayed_write(0, rtc, reg_irq);
 
 	spin_unlock_irqrestore(&rtc->lock, flags);
 
@@ -234,24 +263,23 @@ static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
 	struct armada38x_rtc *rtc = data;
 	u32 val;
 	int event = RTC_IRQF | RTC_AF;
+	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
 
 	dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
 
 	spin_lock(&rtc->lock);
 
-	val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
-
-	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
-	val = read_rtc_register_wa(rtc, RTC_IRQ1_CONF);
-	/* disable all the interrupts for alarm 1 */
-	rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
+	rtc->data->clear_isr(rtc);
+	val = rtc->data->read_rtc_reg(rtc, reg_irq);
+	/* disable all the interrupts for alarm*/
+	rtc_delayed_write(0, rtc, reg_irq);
 	/* Ack the event */
-	rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS);
+	rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
 
 	spin_unlock(&rtc->lock);
 
-	if (val & RTC_IRQ1_FREQ_EN) {
-		if (val & RTC_IRQ1_FREQ_1HZ)
+	if (val & RTC_IRQ_FREQ_EN) {
+		if (val & RTC_IRQ_FREQ_1HZ)
 			event |= RTC_UF;
 		else
 			event |= RTC_PF;
@@ -276,13 +304,37 @@ static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
 	.read_alarm = armada38x_rtc_read_alarm,
 };
 
+static const struct armada38x_rtc_data armada38x_data = {
+	.update_mbus_timing = rtc_update_38x_mbus_timing_params,
+	.read_rtc_reg = read_rtc_register_38x_wa,
+	.clear_isr = armada38x_clear_isr,
+	.unmask_interrupt = armada38x_unmask_interrupt,
+	.alarm = ALARM1,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id armada38x_rtc_of_match_table[] = {
+	{
+		.compatible = "marvell,armada-380-rtc",
+		.data = &armada38x_data,
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
+#endif
+
 static __init int armada38x_rtc_probe(struct platform_device *pdev)
 {
 	const struct rtc_class_ops *ops;
 	struct resource *res;
 	struct armada38x_rtc *rtc;
+	const struct of_device_id *match;
 	int ret;
 
+	match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
+	if (!match)
+		return -ENODEV;
+
 	rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
 			    GFP_KERNEL);
 	if (!rtc)
@@ -327,9 +379,11 @@ static __init int armada38x_rtc_probe(struct platform_device *pdev)
 		 */
 		ops = &armada38x_rtc_ops_noirq;
 	}
+	rtc->data = (struct armada38x_rtc_data *)match->data;
+
 
 	/* Update RTC-MBUS bridge timing parameters */
-	rtc_update_mbus_timing_params(rtc);
+	rtc->data->update_mbus_timing(rtc);
 
 	rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
 						ops, THIS_MODULE);
@@ -359,7 +413,7 @@ static int armada38x_rtc_resume(struct device *dev)
 		struct armada38x_rtc *rtc = dev_get_drvdata(dev);
 
 		/* Update RTC-MBUS bridge timing parameters */
-		rtc_update_mbus_timing_params(rtc);
+		rtc->data->update_mbus_timing(rtc);
 
 		return disable_irq_wake(rtc->irq);
 	}
@@ -371,14 +425,6 @@ static int armada38x_rtc_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
 			 armada38x_rtc_suspend, armada38x_rtc_resume);
 
-#ifdef CONFIG_OF
-static const struct of_device_id armada38x_rtc_of_match_table[] = {
-	{ .compatible = "marvell,armada-380-rtc", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
-#endif
-
 static struct platform_driver armada38x_rtc_driver = {
 	.driver		= {
 		.name	= "armada38x-rtc",
-- 
2.11.0

[PATCH v2 2/3] rtc: armada38x: Add support for Armada 7K/8K

[Gregory CLEMENT]

The Armada 7K/8K use the same RTC IP than the Armada 38x. However the SOC
integration differs in 2 points:
 - MBUS bridge timing initialization
 - IRQ configuration at SoC level

Moreover the Armada 7K/8K have an issue preventing to get the interrupt
from alarm 1. This commit allows to use alarm 2 for these A7K/8K but to
still use alarm 1 for the Armada 38x.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/rtc/armada-380-rtc.txt     |  8 ++-
 drivers/rtc/rtc-armada38x.c                        | 65 ++++++++++++++++++++++
 2 files changed, 70 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
index 2eb9d4ee7dc0..c3c9a1226f9a 100644
--- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
@@ -1,9 +1,11 @@
-* Real Time Clock of the Armada 38x SoCs
+* Real Time Clock of the Armada 38x/7K/8K SoCs
 
-RTC controller for the Armada 38x SoCs
+RTC controller for the Armada 38x, 7K and 8K SoCs
 
 Required properties:
-- compatible : Should be "marvell,armada-380-rtc"
+- compatible : Should be one of the following:
+	"marvell,armada-380-rtc" for Armada 38x SoC
+	"marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
 - reg: a list of base address and size pairs, one for each entry in
   reg-names
 - reg names: should contain:
diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c
index b2a8e2ed71ca..21f355c37eab 100644
--- a/drivers/rtc/rtc-armada38x.c
+++ b/drivers/rtc/rtc-armada38x.c
@@ -24,18 +24,36 @@
 #define RTC_STATUS_ALARM1	    BIT(0)
 #define RTC_STATUS_ALARM2	    BIT(1)
 #define RTC_IRQ1_CONF	    0x4
+#define RTC_IRQ2_CONF	    0x8
 #define RTC_IRQ_AL_EN		    BIT(0)
 #define RTC_IRQ_FREQ_EN		    BIT(1)
 #define RTC_IRQ_FREQ_1HZ	    BIT(2)
 
 #define RTC_TIME	    0xC
 #define RTC_ALARM1	    0x10
+#define RTC_ALARM2	    0x14
+
+/* Armada38x SoC registers  */
 #define RTC_38X_BRIDGE_TIMING_CTL   0x0
 #define RTC_38X_PERIOD_OFFS		0
 #define RTC_38X_PERIOD_MASK		(0x3FF << RTC_38X_PERIOD_OFFS)
 #define RTC_38X_READ_DELAY_OFFS		26
 #define RTC_38X_READ_DELAY_MASK		(0x1F << RTC_38X_READ_DELAY_OFFS)
 
+/* Armada 7K/8K registers  */
+#define RTC_8K_BRIDGE_TIMING_CTL0    0x0
+#define RTC_8K_WRCLK_PERIOD_OFFS	0
+#define RTC_8K_WRCLK_PERIOD_MASK	(0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
+#define RTC_8K_WRCLK_SETUP_OFFS		16
+#define RTC_8K_WRCLK_SETUP_MASK		(0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
+#define RTC_8K_BRIDGE_TIMING_CTL1   0x4
+#define RTC_8K_READ_DELAY_OFFS		0
+#define RTC_8K_READ_DELAY_MASK		(0xFFFF << RTC_8K_READ_DELAY_OFFS)
+
+#define RTC_8K_ISR		    0x10
+#define RTC_8K_IMR		    0x14
+#define RTC_8K_ALARM2			BIT(0)
+
 #define SOC_RTC_INTERRUPT	    0x8
 #define SOC_RTC_ALARM1			BIT(0)
 #define SOC_RTC_ALARM2			BIT(1)
@@ -60,6 +78,8 @@ struct armada38x_rtc {
 };
 
 #define ALARM1	0
+#define ALARM2	1
+
 #define ALARM_REG(base, alarm)	 ((base) + (alarm) * sizeof(u32))
 
 struct armada38x_rtc_data {
@@ -102,6 +122,28 @@ static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
 	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
 }
 
+static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
+{
+	u32 reg;
+
+	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
+	reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
+	reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
+	reg &= ~RTC_8K_WRCLK_SETUP_MASK;
+	reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
+	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
+
+	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
+	reg &= ~RTC_8K_READ_DELAY_MASK;
+	reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
+	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
+}
+
+static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
+{
+	return readl(rtc->regs + rtc_reg);
+}
+
 static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
 {
 	int i, index_max = 0, max = 0;
@@ -157,6 +199,17 @@ static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
 
 	writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
 }
+
+static void armada8k_clear_isr(struct armada38x_rtc *rtc)
+{
+	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
+}
+
+static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
+{
+	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
+}
+
 static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
 {
 	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
@@ -312,12 +365,24 @@ static const struct armada38x_rtc_data armada38x_data = {
 	.alarm = ALARM1,
 };
 
+static const struct armada38x_rtc_data armada8k_data = {
+	.update_mbus_timing = rtc_update_8k_mbus_timing_params,
+	.read_rtc_reg = read_rtc_register,
+	.clear_isr = armada8k_clear_isr,
+	.unmask_interrupt = armada8k_unmask_interrupt,
+	.alarm = ALARM2,
+};
+
 #ifdef CONFIG_OF
 static const struct of_device_id armada38x_rtc_of_match_table[] = {
 	{
 		.compatible = "marvell,armada-380-rtc",
 		.data = &armada38x_data,
 	},
+	{
+		.compatible = "marvell,armada-8k-rtc",
+		.data = &armada8k_data,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
-- 
2.11.0

[PATCH v2 3/3] arm64: dts: marvell: add RTC description for Armada 7K/8K

[Gregory CLEMENT]

This RTC IP is found in the CP110 master and slave which are part of the
Armada 8K SoCs and of the subset family the Armada 7K.

There is one RTC in each CP but the RTC requires an external
oscillator. However on the Armada 80x0, the RTC clock in CP master is not
connected (by package) to the oscillator. So this one is disabled for the
Armada 8020 and the Armada 8040.

As the RTC clock in CP slave is connected to the oscillator this one is
let enabled. and will be used on these SoCs (80x0).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/armada-8020.dtsi         | 10 ++++++++++
 arch/arm64/boot/dts/marvell/armada-8040.dtsi         |  9 +++++++++
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi |  7 +++++++
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  |  7 +++++++
 4 files changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 048e5cf5160e..7c08f1f28d9e 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -54,3 +54,13 @@
 	compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
 		     "marvell,armada-ap806";
 };
+
+/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
+ * in CP master is not connected (by package) to the oscillator. So
+ * disable it. However, the RTC clock in CP slave is connected to the
+ * oscillator so this one is let enabled.
+ */
+
+&cpm_rtc {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 9c1b28c47683..33813a75bc30 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -54,3 +54,12 @@
 	compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
 		     "marvell,armada-ap806";
 };
+
+/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
+ * in CP master is not connected (by package) to the oscillator. So
+ * disable it. However, the RTC clock in CP slave is connected to the
+ * oscillator so this one is let enabled.
+ */
+&cpm_rtc {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 3a99c36433d6..d12741414009 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -79,6 +79,13 @@
 					"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
 			};
 
+			cpm_rtc: rtc at 284000 {
+				compatible = "marvell,armada-8k-rtc";
+				reg = <0x284000 0x20>, <0x284080 0x24>;
+				reg-names = "rtc", "rtc-soc";
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
 			cpm_sata0: sata at 540000 {
 				compatible = "marvell,armada-8k-ahci",
 					     "generic-ahci";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 9e09c4d3b6bd..d01be5a639e9 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -59,6 +59,13 @@
 			interrupt-parent = <&gic>;
 			ranges = <0x0 0x0 0xf4000000 0x2000000>;
 
+			cps_rtc: rtc at 284000 {
+				compatible = "marvell,armada-8k-rtc";
+				reg = <0x284000 0x20>, <0x284080 0x24>;
+				reg-names = "rtc", "rtc-soc";
+				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
 			cps_syscon0: system-controller at 440000 {
 				compatible = "marvell,cp110-system-controller0",
 					     "syscon";
-- 
2.11.0

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Gregory CLEMENT]

Hi,
 
 On ven., f?vr. 17 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:

> The Armada 7K/8K SoCs use the same RTC IP than the Armada 38x. However
> the SOC integration differs in 2 points:
>      - MBUS bridge timing initialization
>      - IRQ configuration at SoC level
>
> This patch set extends the driver support to these SoCs family.
>
> In this second version the device tree was updated allowing to use the
> RTC on Armada 80x0 SoCs. Indeed on the Armada 80x0, the RTC clock in
> CP master is not connected (by package) to the oscillator. So this one
> is disabled for the Armada 8020 and the Armada 8040. On these SoCs it
> will be the RTC clock in CP slave connected to the oscillator which
> will be used.

I saw on IRC than Russell managed to have a more coherent date with this
series on his 8040 based board. For the record, as the U-Boot on this
board didn't provide a "date reset" command for the RTC located on CP
slave, then Russell needed to do the following:

devmem2 0xf428401c w 0
devmem2 0xf4284018 w 0x2000
followed by:
date 021612342017; ntpdate ...; hwclock -uw

But this issue was related to the bootloader not to the kernel. The
other potential issue seen by Russell was about the GIC mapping for the
interrupt, but here again this mapping was done by the 1st stage
bootloader.

Given this information would it be OK to applied this series?

Thanks,

Gregory

>
> Thanks,
>
> Gregory
>
> Gregory CLEMENT (3):
>   rtc: armada38x: Prepare driver to manage different versions
>   rtc: armada38x: Add support for Armada 7K/8K
>   arm64: dts: marvell: add RTC description for Armada 7K/8K
>
>  .../devicetree/bindings/rtc/armada-380-rtc.txt     |   8 +-
>  arch/arm64/boot/dts/marvell/armada-8020.dtsi       |  10 +
>  arch/arm64/boot/dts/marvell/armada-8040.dtsi       |   9 +
>  .../boot/dts/marvell/armada-cp110-master.dtsi      |   7 +
>  .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |   7 +
>  drivers/rtc/rtc-armada38x.c                        | 217 ++++++++++++++++-----
>  6 files changed, 202 insertions(+), 56 deletions(-)
>
> -- 
> 2.11.0
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Russell King - ARM Linux]

On Mon, Feb 20, 2017 at 06:06:11PM +0100, Gregory CLEMENT wrote:
> I saw on IRC than Russell managed to have a more coherent date with this
> series on his 8040 based board. For the record, as the U-Boot on this
> board didn't provide a "date reset" command for the RTC located on CP
> slave, then Russell needed to do the following:
> 
> devmem2 0xf428401c w 0
> devmem2 0xf4284018 w 0x2000
> followed by:
> date 021612342017; ntpdate ...; hwclock -uw
> 
> But this issue was related to the bootloader not to the kernel. The
> other potential issue seen by Russell was about the GIC mapping for the
> interrupt, but here again this mapping was done by the 1st stage
> bootloader.
> 
> Given this information would it be OK to applied this series?

No it is not.  As I already pointed out, the interrupt for the 8040 is
GIC_SPI 71 _not_ GIC_SPI 77 as you have it in this series.

Both CP110's on Armada 8040 have a default mapping of ICU 77 to GIC 71.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
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[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Gregory CLEMENT]

Hi Russell King,
 
 On lun., f?vr. 20 2017, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:

> On Mon, Feb 20, 2017 at 06:06:11PM +0100, Gregory CLEMENT wrote:
>> I saw on IRC than Russell managed to have a more coherent date with this
>> series on his 8040 based board. For the record, as the U-Boot on this
>> board didn't provide a "date reset" command for the RTC located on CP
>> slave, then Russell needed to do the following:
>> 
>> devmem2 0xf428401c w 0
>> devmem2 0xf4284018 w 0x2000
>> followed by:
>> date 021612342017; ntpdate ...; hwclock -uw
>> 
>> But this issue was related to the bootloader not to the kernel. The
>> other potential issue seen by Russell was about the GIC mapping for the
>> interrupt, but here again this mapping was done by the 1st stage
>> bootloader.
>> 
>> Given this information would it be OK to applied this series?
>
> No it is not.  As I already pointed out, the interrupt for the 8040 is
> GIC_SPI 71 _not_ GIC_SPI 77 as you have it in this series.
>
> Both CP110's on Armada 8040 have a default mapping of ICU 77 to GIC
> 71.

OK so I am sending a v2 with this fix.

Thanks,

Gregory

>
> -- 
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> according to speedtest.net.

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Alexandre Belloni]

On 20/02/2017 at 18:06:11 +0100, Gregory CLEMENT wrote:
>  On ven., f?vr. 17 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> 
> > The Armada 7K/8K SoCs use the same RTC IP than the Armada 38x. However
> > the SOC integration differs in 2 points:
> >      - MBUS bridge timing initialization
> >      - IRQ configuration at SoC level
> >
> > This patch set extends the driver support to these SoCs family.
> >
> > In this second version the device tree was updated allowing to use the
> > RTC on Armada 80x0 SoCs. Indeed on the Armada 80x0, the RTC clock in
> > CP master is not connected (by package) to the oscillator. So this one
> > is disabled for the Armada 8020 and the Armada 8040. On these SoCs it
> > will be the RTC clock in CP slave connected to the oscillator which
> > will be used.
> 
> I saw on IRC than Russell managed to have a more coherent date with this
> series on his 8040 based board. For the record, as the U-Boot on this
> board didn't provide a "date reset" command for the RTC located on CP
> slave, then Russell needed to do the following:
> 
> devmem2 0xf428401c w 0
> devmem2 0xf4284018 w 0x2000

The question being what does that do and whether it could be done in the
driver instead.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Russell King - ARM Linux]

On Mon, Feb 20, 2017 at 05:27:39PM +0000, Russell King - ARM Linux wrote:
> No it is not.  As I already pointed out, the interrupt for the 8040 is
> GIC_SPI 71 _not_ GIC_SPI 77 as you have it in this series.
> 
> Both CP110's on Armada 8040 have a default mapping of ICU 77 to GIC 71.

For reference, here's the full boot-time mapping of the ICU.  I don't
know what's responsible for this mapping, but this is read directly
out of the ICU at kernel boot.

Format of the following table is:

ICU-irq => GIC-SPI-num Enable Edge/Level ICU-group

ICU mapping (/cp110-master/config-space at f2000000/interrupt-controller at 1e0000)
    0 =>  32    Lv 0
    1 =>  32    Lv 0
    2 =>  32    Lv 0
    3 =>  32    Lv 0
    4 =>  32    Lv 0
    5 =>  32    Lv 0
    6 =>  32    Lv 0
    7 =>  32    Lv 0
    8 =>  32    Lv 0
    9 =>  32    Lv 0
   10 =>  32    Lv 0
   11 =>  53 En Lv 4
   12 =>  32 En Lv 5
   13 =>  32    Lv 0
   14 =>  32    Lv 0
   15 =>  54 En Lv 4
   16 =>  55 En Lv 4
   17 =>  56 En Lv 4
   18 =>  57 En Lv 4
   19 =>  58 En Lv 4
   20 =>  59 En Lv 4
   21 =>  60 En Lv 4
   22 =>  32 En Lv 0
   23 =>  33 En Lv 0
   24 =>  34 En Lv 0
   25 =>  61 En Lv 4
   26 =>  33 En Lv 5
   27 =>  69 En Lv 0
   28 =>  32    Lv 0
   29 =>  32    Lv 0
   30 =>  32    Lv 0
   31 =>  32    Lv 0
   32 =>  32    Lv 0
   33 =>  35 En Lv 0
   34 =>  35 En Lv 0
   35 =>  35 En Lv 0
   36 =>  35 En Lv 0
   37 =>  32    Lv 0
   38 =>  36 En Lv 0
   39 =>  37 En Lv 0
   40 =>  38 En Lv 0
   41 =>  39 En Lv 0
   42 =>  40 En Lv 0
   43 =>  41 En Lv 0
   44 =>  42 En Lv 0
   45 =>  43 En Lv 0
   46 =>  44 En Lv 0
   47 =>  45 En Lv 0
   48 =>  46 En Lv 0
   49 =>  47 En Lv 0
   50 =>  48 En Lv 0
   51 =>  49 En Lv 0
   52 =>  50 En Lv 0
   53 =>  51 En Lv 0
   54 =>  52 En Lv 0
   55 =>  92 En Lv 0
   56 =>  93 En Lv 0
   57 =>  94 En Lv 0
   58 =>  95 En Lv 0
   59 =>  32    Lv 0
   60 =>  32    Lv 0
   61 =>  32    Lv 0
   62 =>  32    Lv 0
   63 =>  32    Lv 0
   64 =>  32    Lv 0
   65 =>  32    Lv 0
   66 =>  32    Lv 0
   67 =>  32    Lv 0
   68 =>  32    Lv 0
   69 =>  32    Lv 0
   70 =>  32    Lv 0
   71 =>  32    Lv 0
   72 =>  32    Lv 0
   73 =>  32    Lv 0
   74 =>  32    Lv 0
   75 =>  62 En Lv 4
   76 =>  70 En Lv 0
   77 =>  71 En Lv 0
   78 =>  53 En Lv 0
   79 =>  72 En Lv 0
   80 =>  73 En Lv 0
   81 =>  74 En Lv 0
   82 =>  75 En Lv 0
   83 =>  76 En Lv 0
   84 =>  77 En Lv 0
   85 =>  78 En Lv 0
   86 =>  79 En Lv 0
   87 =>  34 En Lv 5
   88 =>  54 En Lv 0
   89 =>  55 En Lv 0
   90 =>  56 En Lv 0
   91 =>  57 En Lv 0
   92 =>  58 En Lv 0
   93 =>  35 En Ed 5
   94 =>  63 En Lv 4
   95 =>  59 En Lv 0
   96 =>  36 En Lv 5
   97 =>  64 En Lv 4
   98 =>  37 En Lv 5
   99 =>  65 En Lv 4
  100 =>  38 En Ed 5
  101 =>  39 En Ed 5
  102 =>  60 En Lv 0
  103 =>  40 En Ed 5
  104 =>  41 En Ed 5
  105 =>  61 En Lv 0
  106 =>  62 En Lv 0
  107 =>  63 En Lv 0
  108 =>  66 En Lv 4
  109 =>  63 En Lv 0
  110 =>  67 En Lv 4
  111 =>  80 En Lv 0
  112 =>  81 En Lv 0
  113 =>  82 En Lv 0
  114 =>  68 En Lv 4
  115 =>  83 En Lv 0
  116 =>  69 En Lv 4
  117 =>  70 En Lv 4
  118 =>  85 En Lv 0
  119 =>  32    Lv 0
  120 =>  86 En Lv 0
  121 =>  87 En Lv 0
  122 =>  88 En Lv 0
  123 =>  89 En Lv 0
  124 =>  90 En Lv 0
  125 =>  91 En Lv 0
  126 =>  65 En Lv 0
  127 =>  66 En Lv 0
  128 =>  67 En Lv 0
  129 =>  68 En Lv 0
ICU mapping (/cp110-slave/config-space at f4000000/interrupt-controller at 1e0000)
    0 =>  32    Lv 0
    1 =>  32    Lv 0
    2 =>  32    Lv 0
    3 =>  32    Lv 0
    4 =>  32    Lv 0
    5 =>  32    Lv 0
    6 =>  32    Lv 0
    7 =>  32    Lv 0
    8 =>  32    Lv 0
    9 =>  32    Lv 0
   10 =>  32    Lv 0
   11 =>  53 En Lv 4
   12 =>  32 En Lv 5
   13 =>  32    Lv 0
   14 =>  32    Lv 0
   15 =>  54 En Lv 4
   16 =>  55 En Lv 4
   17 =>  56 En Lv 4
   18 =>  57 En Lv 4
   19 =>  58 En Lv 4
   20 =>  59 En Lv 4
   21 =>  60 En Lv 4
   22 => 256 En Lv 0
   23 => 257 En Lv 0
   24 => 258 En Lv 0
   25 =>  61 En Lv 4
   26 =>  33 En Lv 5
   27 =>  69 En Lv 0
   28 =>  32    Lv 0
   29 =>  32    Lv 0
   30 =>  32    Lv 0
   31 =>  32    Lv 0
   32 =>  32    Lv 0
   33 => 259 En Lv 0
   34 => 259 En Lv 0
   35 => 259 En Lv 0
   36 => 259 En Lv 0
   37 =>  32    Lv 0
   38 => 260 En Lv 0
   39 => 261 En Lv 0
   40 => 262 En Lv 0
   41 => 263 En Lv 0
   42 => 264 En Lv 0
   43 => 265 En Lv 0
   44 => 266 En Lv 0
   45 => 267 En Lv 0
   46 => 268 En Lv 0
   47 => 269 En Lv 0
   48 => 270 En Lv 0
   49 => 271 En Lv 0
   50 => 272 En Lv 0
   51 => 273 En Lv 0
   52 => 274 En Lv 0
   53 => 275 En Lv 0
   54 => 276 En Lv 0
   55 => 316 En Lv 0
   56 => 317 En Lv 0
   57 => 318 En Lv 0
   58 => 319 En Lv 0
   59 =>  32    Lv 0
   60 =>  32    Lv 0
   61 =>  32    Lv 0
   62 =>  32    Lv 0
   63 =>  32    Lv 0
   64 =>  32    Lv 0
   65 =>  32    Lv 0
   66 =>  32    Lv 0
   67 =>  32    Lv 0
   68 =>  32    Lv 0
   69 =>  32    Lv 0
   70 =>  32    Lv 0
   71 =>  32    Lv 0
   72 =>  32    Lv 0
   73 =>  32    Lv 0
   74 =>  32    Lv 0
   75 =>  62 En Lv 4
   76 =>  70 En Lv 0
   77 =>  71 En Lv 0
   78 => 277 En Lv 0
   79 =>  72 En Lv 0
   80 =>  73 En Lv 0
   81 =>  74 En Lv 0
   82 =>  75 En Lv 0
   83 =>  76 En Lv 0
   84 =>  77 En Lv 0
   85 =>  78 En Lv 0
   86 =>  79 En Lv 0
   87 =>  34 En Lv 5
   88 => 278 En Lv 0
   89 => 279 En Lv 0
   90 => 280 En Lv 0
   91 => 281 En Lv 0
   92 => 282 En Lv 0
   93 =>  35 En Ed 5
   94 =>  63 En Lv 4
   95 => 283 En Lv 0
   96 =>  36 En Lv 5
   97 =>  64 En Lv 4
   98 =>  37 En Lv 5
   99 =>  65 En Lv 4
  100 =>  38 En Ed 5
  101 =>  39 En Ed 5
  102 => 284 En Lv 0
  103 =>  40 En Ed 5
  104 =>  41 En Ed 5
  105 => 285 En Lv 0
  106 => 286 En Lv 0
  107 => 287 En Lv 0
  108 =>  66 En Lv 4
  109 => 287 En Lv 0
  110 =>  67 En Lv 4
  111 =>  80 En Lv 0
  112 =>  81 En Lv 0
  113 =>  82 En Lv 0
  114 =>  68 En Lv 4
  115 =>  83 En Lv 0
  116 =>  69 En Lv 4
  117 =>  70 En Lv 4
  118 =>  85 En Lv 0
  119 =>  32    Lv 0
  120 =>  86 En Lv 0
  121 =>  87 En Lv 0
  122 =>  88 En Lv 0
  123 =>  89 En Lv 0
  124 =>  90 En Lv 0
  125 =>  91 En Lv 0
  126 => 289 En Lv 0
  127 => 290 En Lv 0
  128 => 291 En Lv 0
  129 => 292 En Lv 0

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Gregory CLEMENT]

Hi Alexandre,
 
 On lun., f?vr. 20 2017, Alexandre Belloni <alexandre.belloni@free-electrons.com> wrote:

> On 20/02/2017 at 18:06:11 +0100, Gregory CLEMENT wrote:
>>  On ven., f?vr. 17 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
>> 
>> > The Armada 7K/8K SoCs use the same RTC IP than the Armada 38x. However
>> > the SOC integration differs in 2 points:
>> >      - MBUS bridge timing initialization
>> >      - IRQ configuration at SoC level
>> >
>> > This patch set extends the driver support to these SoCs family.
>> >
>> > In this second version the device tree was updated allowing to use the
>> > RTC on Armada 80x0 SoCs. Indeed on the Armada 80x0, the RTC clock in
>> > CP master is not connected (by package) to the oscillator. So this one
>> > is disabled for the Armada 8020 and the Armada 8040. On these SoCs it
>> > will be the RTC clock in CP slave connected to the oscillator which
>> > will be used.
>> 
>> I saw on IRC than Russell managed to have a more coherent date with this
>> series on his 8040 based board. For the record, as the U-Boot on this
>> board didn't provide a "date reset" command for the RTC located on CP
>> slave, then Russell needed to do the following:
>> 
>> devmem2 0xf428401c w 0
>> devmem2 0xf4284018 w 0x2000
>
> The question being what does that do and whether it could be done in the
> driver instead.

The first time the RTC is powered up it needed to be reset. It is the
purpose of these 2 lines. As it should be done only one time when a the
RTC is powered of the first time it was chosen to be done in the
bootloader.

Maybe later it could be part of the kernel, as an optional parameter for
instance, but currently I don't know if there is more involved when
resetting the RTC.

Gregory



>
> -- 
> Alexandre Belloni, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Russell King - ARM Linux]

On Mon, Feb 20, 2017 at 06:36:33PM +0100, Alexandre Belloni wrote:
> On 20/02/2017 at 18:06:11 +0100, Gregory CLEMENT wrote:
> >  On ven., f?vr. 17 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> > 
> > > The Armada 7K/8K SoCs use the same RTC IP than the Armada 38x. However
> > > the SOC integration differs in 2 points:
> > >      - MBUS bridge timing initialization
> > >      - IRQ configuration at SoC level
> > >
> > > This patch set extends the driver support to these SoCs family.
> > >
> > > In this second version the device tree was updated allowing to use the
> > > RTC on Armada 80x0 SoCs. Indeed on the Armada 80x0, the RTC clock in
> > > CP master is not connected (by package) to the oscillator. So this one
> > > is disabled for the Armada 8020 and the Armada 8040. On these SoCs it
> > > will be the RTC clock in CP slave connected to the oscillator which
> > > will be used.
> > 
> > I saw on IRC than Russell managed to have a more coherent date with this
> > series on his 8040 based board. For the record, as the U-Boot on this
> > board didn't provide a "date reset" command for the RTC located on CP
> > slave, then Russell needed to do the following:
> > 
> > devmem2 0xf428401c w 0
> > devmem2 0xf4284018 w 0x2000
> 
> The question being what does that do and whether it could be done in the
> driver instead.

It's not specific to the Armada 8040, the same problem exists with
Armada 38x, so holding this up for that reason does not make sense.

>From what I've been told via SolidRun, it's an errata work-around.
Armada 38x needs "date reset" to be given _twice_ in uboot if the
RTC is not functioning, and part of the "date reset" sequence is
the above couple of register writes.

What effect it would have on an already running RTC is not known -
but using "date reset" in uboot for a correct RTC has the effect of
setting it back to 1970.

On Armada 38x:

Table 1461: RTC Clock Correction Register   Offset:   0x000A3818
Bit         Field                Type / InitVal  Description
31:16       Reserved             RSVD   0x0      Reserved
15          Correct Mode         RW     0x0      Correction Mode
                                                 0 = Low
                                                 1 = High
14:0        Correct Value        RW     0x0      Correction Value

Table 1462: RTC Test Configuration Register Offset:   0x000A381C
Bit         Field                Type / InitVal   Description
31:5        Reserved             RSVD   0x0       Reserved
4           Func Test            RW     0x0       Functional Test Acceleration
3:0         Reserved             RSVD   0x0       Reserved

So, we don't know what the first write really does.

I suspect that the errata is "RTC is not reset at power up" for the RTC
power domain.

I don't know where the value of 0x2000 comes from for the correction
value, all I know is that's the value uboot uses with "date reset".
We probably do _not_ want the driver writing that each time the
kernel boots, since that's a tuning parameter.

This is all purely guesswork though.

-- 
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[PATCH v2 0/3] Extend rtc-armada38x support for Armada 7K/8K

[Alexandre Belloni]

On 20/02/2017 at 17:50:54 +0000, Russell King - ARM Linux wrote:
> > The question being what does that do and whether it could be done in the
> > driver instead.
> 
> It's not specific to the Armada 8040, the same problem exists with
> Armada 38x, so holding this up for that reason does not make sense.
> 

I agree, I will not delay the patch for that.

> I suspect that the errata is "RTC is not reset at power up" for the RTC
> power domain.
> 
> I don't know where the value of 0x2000 comes from for the correction
> value, all I know is that's the value uboot uses with "date reset".
> We probably do _not_ want the driver writing that each time the
> kernel boots, since that's a tuning parameter.
> 

It is probably a calibration offset. It may be worth exposing to
userspace but without more information, I doubt we can make something
useful out of it.



-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com