* [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11
@ 2013-05-29 16:38 Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common header for re-use Santosh Shilimkar
` (13 more replies)
0 siblings, 14 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
Tony, Paul,
Here is another attempt to send the SOC data files for OMAP5 based devices.
As aligned on list, I have dropped clock data from the series.
That means for the boot, one clock data patch needs to be applied.
It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.
With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
is also targeted as DT only, its hwmod data files is also cleaned up.
Diffstat looks something like below.
27 files changed, 9013 insertions(+), 2764 deletions(-)
One can easily notice that the OMAP5 SOC data has significantly come down
becasue of iospace and rest of the hwmod clean-up.
Thanks to Sricharan, Vaibhav Bedia, Vaibhav H, Rajendra and Benoit for the
patches and testing.
The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:
Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux.git for_3.11/omap5_data_files
for you to fetch changes up to 86b6a6dd106973df7f0c097fcb252e9e54b2f971:
ARM: OMAP4: hwmod data: Clean up the data file (2013-05-29 11:51:30 -0400)
----------------------------------------------------------------
Benoit Cousson (7):
ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
ARM: OMAP5: SCRM: Add OMAP54XX header file.
ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header
ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Santosh Shilimkar (5):
ARM: OMAP4+: PRM: Move function prototypes to common header for
re-use
ARM: OMAP4+: CM: Move function prototypes to common header for re-use
ARM: OMAP4+: PRCM MPU: Move function prototypes to common header for
re-use
ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
ARM: OMAP5: Enable build and frameowrk initialisations
Sricharan R (1):
ARM: OMAP4: hwmod data: Clean up the data file
Vaibhav Hiremath (1):
ARM: AM33XX: hwmod data: irq, dma and addr info clean up
arch/arm/mach-omap2/Makefile | 4 +
arch/arm/mach-omap2/clockdomain.h | 1 +
arch/arm/mach-omap2/clockdomains54xx_data.c | 464 +++++
arch/arm/mach-omap2/cm-regbits-54xx.h | 1737 ++++++++++++++++
arch/arm/mach-omap2/cm1_44xx.h | 7 +-
arch/arm/mach-omap2/cm1_54xx.h | 218 ++
arch/arm/mach-omap2/cm2_44xx.h | 7 +-
arch/arm/mach-omap2/cm2_54xx.h | 394 ++++
arch/arm/mach-omap2/cm_44xx_54xx.h | 36 +
arch/arm/mach-omap2/io.c | 7 +
arch/arm/mach-omap2/omap_hwmod.h | 1 +
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1067 ----------
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1661 +--------------
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2151 ++++++++++++++++++++
arch/arm/mach-omap2/powerdomain.h | 1 +
arch/arm/mach-omap2/powerdomains54xx_data.c | 331 +++
arch/arm/mach-omap2/prcm44xx.h | 6 +
arch/arm/mach-omap2/prcm_mpu44xx.h | 14 +-
arch/arm/mach-omap2/prcm_mpu54xx.h | 87 +
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h | 36 +
arch/arm/mach-omap2/prm-regbits-54xx.h | 2701 +++++++++++++++++++++++++
arch/arm/mach-omap2/prm44xx.h | 33 +-
arch/arm/mach-omap2/prm44xx_54xx.h | 58 +
arch/arm/mach-omap2/prm54xx.h | 421 ++++
arch/arm/mach-omap2/scrm54xx.h | 231 +++
arch/arm/mach-omap2/voltage.h | 1 +
arch/arm/mach-omap2/voltagedomains54xx_data.c | 102 +
27 files changed, 9013 insertions(+), 2764 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c
create mode 100644 arch/arm/mach-omap2/cm-regbits-54xx.h
create mode 100644 arch/arm/mach-omap2/cm1_54xx.h
create mode 100644 arch/arm/mach-omap2/cm2_54xx.h
create mode 100644 arch/arm/mach-omap2/cm_44xx_54xx.h
create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c
create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c
create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h
create mode 100644 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
create mode 100644 arch/arm/mach-omap2/prm-regbits-54xx.h
create mode 100644 arch/arm/mach-omap2/prm44xx_54xx.h
create mode 100644 arch/arm/mach-omap2/prm54xx.h
create mode 100644 arch/arm/mach-omap2/scrm54xx.h
create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common header for re-use
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 03/14] ARM: OMAP4+: CM: " Santosh Shilimkar
` (12 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
OMAP5 reuses OMAP4 PRM IP block which lets us re-use PRM functions.
So move the function prototypes from prm44xx.h to prm44xx_54xx.h
header. The suggestion came from Paul Walmsley as part of the
OMAP5 data file review.
This is preparatory patch to add OMAP5 PRM data file.
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/prm44xx.h | 33 +-------------------
arch/arm/mach-omap2/prm44xx_54xx.h | 58 ++++++++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+), 32 deletions(-)
create mode 100644 arch/arm/mach-omap2/prm44xx_54xx.h
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbd..7db2422 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
@@ -744,36 +745,4 @@
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-/* OMAP4-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP4 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-extern void omap44xx_prm_reconfigure_io_chain(void);
-
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-
-extern int __init omap44xx_prm_init(void);
-extern u32 omap44xx_prm_get_reset_sources(void);
-
-# endif
-
#endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 0000000..7cd22ab
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
+
+#endif
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 03/14] ARM: OMAP4+: CM: Move function prototypes to common header for re-use
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common header for re-use Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-06-08 17:44 ` Paul Walmsley
2013-05-29 16:38 ` [PATCH 05/14] ARM: OMAP4+: PRCM MPU: " Santosh Shilimkar
` (11 subsequent siblings)
13 siblings, 1 reply; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
OMAP5 reuses OMAP4 CM IP block which lets us re-use CM1/CM2 functions.
So move the function prototypes from cm1_44xx.h, cm2_44xx.h to
cm_prm44xx_54xx.h header. The suggestion came from Paul Walmsley
as part of the OMAP5 data file review.
This is preparatory patch to add OMAP5 CM data file.
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/cm1_44xx.h | 7 ++-----
arch/arm/mach-omap2/cm2_44xx.h | 7 ++-----
arch/arm/mach-omap2/cm_44xx_54xx.h | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 40 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/mach-omap2/cm_44xx_54xx.h
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc..5ae8fe3 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+#include "cm_44xx_54xx.h"
+
/* CM1 base address */
#define OMAP4430_CM1_BASE 0x4a004000
@@ -217,9 +219,4 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
-/* Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72d..ee5136d 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+#include "cm_44xx_54xx.h"
+
/* CM2 base address */
#define OMAP4430_CM2_BASE 0x4a008000
@@ -449,9 +451,4 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
-/* Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
#endif
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 0000000..4154f86
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
+ *
+ * Copyright (C) 2009-201333 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
+
+/* CM1 Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* CM2 Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 05/14] ARM: OMAP4+: PRCM MPU: Move function prototypes to common header for re-use
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common header for re-use Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 03/14] ARM: OMAP4+: CM: " Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 06/14] ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers Santosh Shilimkar
` (10 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
OMAP5 reuses OMAP4 MPU PRCM IP block which lets us re-use functions.
So move the function prototypes from prcm_mpu44xx.h to prcm_mpu_44xx_54xx.h
header. The suggestion came from Paul Walmsley as part of the
OMAP5 data file review.
This is preparatory patch to add OMAP5 MPU PRCM data file.
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/prcm_mpu44xx.h | 14 +-----------
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h | 36 ++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7b..059bd4f 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+#include "prcm_mpu_44xx_54xx.h"
#include "common.h"
-# ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-# endif
-
#define OMAP4430_PRCM_MPU_BASE 0x48243000
#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
- s16 idx);
-extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
-# endif
-
#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 0000000..ca149e7
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx PRCM MPU function prototypes
+ *
+ * Copyright (C) 2010, 2013 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+
+#ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+ s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
+#endif
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 06/14] ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (2 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 05/14] ARM: OMAP4+: PRCM MPU: " Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 07/14] ARM: OMAP5: SCRM: Add OMAP54XX header file Santosh Shilimkar
` (9 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Add the PRCM MPU registers for OMAP54XX platforms.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/prcm44xx.h | 6 +++
arch/arm/mach-omap2/prcm_mpu54xx.h | 87 ++++++++++++++++++++++++++++++++++++
2 files changed, 93 insertions(+)
create mode 100644 arch/arm/mach-omap2/prcm_mpu54xx.h
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb..f429cdd 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
#define OMAP4430_SCRM_PARTITION 4
#define OMAP4430_PRCM_MPU_PARTITION 5
+#define OMAP54XX_PRM_PARTITION 1
+#define OMAP54XX_CM_CORE_AON_PARTITION 2
+#define OMAP54XX_CM_CORE_PARTITION 3
+#define OMAP54XX_SCRM_PARTITION 4
+#define OMAP54XX_PRCM_MPU_PARTITION 5
+
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 0000000..bc2ce32
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
+/*
+ * OMAP54xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ * Rajendra Nayak (rnayak at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+
+#include "prcm_mpu_44xx_54xx.h"
+#include "common.h"
+
+#define OMAP54XX_PRCM_MPU_BASE 0x48243000
+
+#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
+#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
+#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
+#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
+#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
+#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
+#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
+#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
+
+/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
+#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
+#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
+#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
+#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+
+/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
+#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
+#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
+#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
+#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
+#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
+#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
+
+/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
+#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
+#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
+#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
+#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
+#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
+#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 07/14] ARM: OMAP5: SCRM: Add OMAP54XX header file.
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (3 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 06/14] ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 08/14] ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header Santosh Shilimkar
` (8 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Adding the OMAP5 specific header for SCRM module.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/scrm54xx.h | 231 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
create mode 100644 arch/arm/mach-omap2/scrm54xx.h
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 0000000..57e86c8
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
+/*
+ * OMAP54XX SCRM registers and bitfields
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+
+#define OMAP5_SCRM_BASE 0x4ae0a000
+
+#define OMAP54XX_SCRM_REGADDR(reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
+
+/* SCRM */
+
+/* SCRM.SCRM register offsets */
+#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
+#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
+#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
+#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
+#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
+#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
+#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
+#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
+#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
+#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
+#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
+#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
+#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
+#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
+#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
+#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
+#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
+#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
+#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
+#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
+#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
+#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
+#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
+#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
+#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
+#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
+#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
+#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
+#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
+#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
+#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
+#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
+#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
+#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
+#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
+#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
+#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
+#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
+#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
+#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
+#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
+#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
+#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
+#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
+#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
+#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
+#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
+#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
+#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
+#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
+#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
+#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
+#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
+#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
+#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
+#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
+#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
+#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
+#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
+#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5, D2DCLKREQ
+ */
+#define OMAP5_ACCURACY_SHIFT 1
+#define OMAP5_ACCURACY_WIDTH 0x1
+#define OMAP5_ACCURACY_MASK (1 << 1)
+
+/* Used by APEWARMRSTST */
+#define OMAP5_APEWARMRSTST_SHIFT 1
+#define OMAP5_APEWARMRSTST_WIDTH 0x1
+#define OMAP5_APEWARMRSTST_MASK (1 << 1)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_CLKDIV_SHIFT 16
+#define OMAP5_CLKDIV_WIDTH 0x4
+#define OMAP5_CLKDIV_MASK (0xf << 16)
+
+/* Used by D2DCLKM, MODEMCLKM */
+#define OMAP5_CLK_32KHZ_SHIFT 0
+#define OMAP5_CLK_32KHZ_WIDTH 0x1
+#define OMAP5_CLK_32KHZ_MASK (1 << 0)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_COLDRST_SHIFT 0
+#define OMAP5_COLDRST_WIDTH 0x1
+#define OMAP5_COLDRST_MASK (1 << 0)
+
+/* Used by D2DWARMRSTST */
+#define OMAP5_D2DWARMRSTST_SHIFT 3
+#define OMAP5_D2DWARMRSTST_WIDTH 0x1
+#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
+
+/* Used by AUXCLK0 */
+#define OMAP5_DISABLECLK_SHIFT 9
+#define OMAP5_DISABLECLK_WIDTH 0x1
+#define OMAP5_DISABLECLK_MASK (1 << 9)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_DOWNTIME_SHIFT 16
+#define OMAP5_DOWNTIME_WIDTH 0x6
+#define OMAP5_DOWNTIME_MASK (0x3f << 16)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_ENABLE_SHIFT 8
+#define OMAP5_ENABLE_WIDTH 0x1
+#define OMAP5_ENABLE_MASK (1 << 8)
+
+/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
+#define OMAP5_ENABLE_0_0_SHIFT 0
+#define OMAP5_ENABLE_0_0_WIDTH 0x1
+#define OMAP5_ENABLE_0_0_MASK (1 << 0)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_EXT_SHIFT 3
+#define OMAP5_ENABLE_EXT_WIDTH 0x1
+#define OMAP5_ENABLE_EXT_MASK (1 << 3)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_INT_SHIFT 2
+#define OMAP5_ENABLE_INT_WIDTH 0x1
+#define OMAP5_ENABLE_INT_MASK (1 << 2)
+
+/* Used by EXTWARMRSTST */
+#define OMAP5_EXTWARMRSTST_SHIFT 0
+#define OMAP5_EXTWARMRSTST_WIDTH 0x1
+#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5
+ */
+#define OMAP5_MAPPING_SHIFT 2
+#define OMAP5_MAPPING_WIDTH 0x3
+#define OMAP5_MAPPING_MASK (0x7 << 2)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_MODE_SHIFT 0
+#define OMAP5_MODE_WIDTH 0x2
+#define OMAP5_MODE_MASK (0x3 << 0)
+
+/* Used by MODEMWARMRSTST */
+#define OMAP5_MODEMWARMRSTST_SHIFT 2
+#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
+#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
+
+/*
+ * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
+ * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
+ * D2DCLKREQ, EXTCLKREQ, PWRREQ
+ */
+#define OMAP5_POLARITY_SHIFT 0
+#define OMAP5_POLARITY_WIDTH 0x1
+#define OMAP5_POLARITY_MASK (1 << 0)
+
+/* Used by EXTPWRONRSTCTRL */
+#define OMAP5_PWRONRST_SHIFT 1
+#define OMAP5_PWRONRST_WIDTH 0x1
+#define OMAP5_PWRONRST_MASK (1 << 1)
+
+/* Used by REVISION_SCRM */
+#define OMAP5_REV_SHIFT 0
+#define OMAP5_REV_WIDTH 0x8
+#define OMAP5_REV_MASK (0xff << 0)
+
+/* Used by RSTTIME */
+#define OMAP5_RSTTIME_SHIFT 0
+#define OMAP5_RSTTIME_WIDTH 0x4
+#define OMAP5_RSTTIME_MASK (0xf << 0)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_SETUPTIME_SHIFT 0
+#define OMAP5_SETUPTIME_WIDTH 0xc
+#define OMAP5_SETUPTIME_MASK (0xfff << 0)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_SLEEPTIME_SHIFT 0
+#define OMAP5_SLEEPTIME_WIDTH 0x6
+#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_SRCSELECT_SHIFT 1
+#define OMAP5_SRCSELECT_WIDTH 0x2
+#define OMAP5_SRCSELECT_MASK (0x3 << 1)
+
+/* Used by D2DCLKM */
+#define OMAP5_SYSCLK_SHIFT 1
+#define OMAP5_SYSCLK_WIDTH 0x1
+#define OMAP5_SYSCLK_MASK (1 << 1)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_WAKEUPTIME_SHIFT 16
+#define OMAP5_WAKEUPTIME_WIDTH 0x6
+#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_WARMRST_SHIFT 1
+#define OMAP5_WARMRST_WIDTH 0x1
+#define OMAP5_WARMRST_MASK (1 << 1)
+
+#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 08/14] ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (4 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 07/14] ARM: OMAP5: SCRM: Add OMAP54XX header file Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 09/14] ARM: OMAP5: powerdomain " Santosh Shilimkar
` (7 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Add the data file to describe all clock domains inside the OMAP54XX soc.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/clockdomain.h | 1 +
arch/arm/mach-omap2/clockdomains54xx_data.c | 464 +++++++++++++++++++++++++++
2 files changed, 465 insertions(+)
create mode 100644 arch/arm/mach-omap2/clockdomains54xx_data.c
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da3765..daeecf1 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
+extern void __init omap54xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 0000000..1a3c69d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
+/*
+ * OMAP54XX Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu54xx.h"
+
+/* Static Dependencies for OMAP4 Clock Domains */
+
+static struct clkdm_dep c2c_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dsp_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep ipu_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "dsp_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "abe_clkdm" },
+ { .clkdm_name = "dsp_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l3main2_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clockdomain l4sec_54xx_clkdm = {
+ .name = "l4sec_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
+ .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
+ .wkdep_srcs = l4sec_wkup_sleep_deps,
+ .sleepdep_srcs = l4sec_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain iva_54xx_clkdm = {
+ .name = "iva_clkdm",
+ .pwrdm = { .name = "iva_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_IVA_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
+ .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
+ .wkdep_srcs = iva_wkup_sleep_deps,
+ .sleepdep_srcs = iva_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mipiext_54xx_clkdm = {
+ .name = "mipiext_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
+ .wkdep_srcs = mipiext_wkup_sleep_deps,
+ .sleepdep_srcs = mipiext_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main2_54xx_clkdm = {
+ .name = "l3main2_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
+ .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main1_54xx_clkdm = {
+ .name = "l3main1_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+ .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_54xx_clkdm = {
+ .name = "custefuse_clkdm",
+ .pwrdm = { .name = "custefuse_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_54xx_clkdm = {
+ .name = "ipu_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
+ .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
+ .wkdep_srcs = ipu_wkup_sleep_deps,
+ .sleepdep_srcs = ipu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_54xx_clkdm = {
+ .name = "l4cfg_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
+ .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain abe_54xx_clkdm = {
+ .name = "abe_clkdm",
+ .pwrdm = { .name = "abe_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
+ .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_54xx_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_DSS_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
+ .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
+ .wkdep_srcs = dss_wkup_sleep_deps,
+ .sleepdep_srcs = dss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp_54xx_clkdm = {
+ .name = "dsp_clkdm",
+ .pwrdm = { .name = "dsp_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
+ .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
+ .wkdep_srcs = dsp_wkup_sleep_deps,
+ .sleepdep_srcs = dsp_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain c2c_54xx_clkdm = {
+ .name = "c2c_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
+ .wkdep_srcs = c2c_wkup_sleep_deps,
+ .sleepdep_srcs = c2c_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l4per_54xx_clkdm = {
+ .name = "l4per_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
+ .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_54xx_clkdm = {
+ .name = "gpu_clkdm",
+ .pwrdm = { .name = "gpu_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_GPU_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
+ .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
+ .wkdep_srcs = gpu_wkup_sleep_deps,
+ .sleepdep_srcs = gpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_54xx_clkdm = {
+ .name = "wkupaon_clkdm",
+ .pwrdm = { .name = "wkupaon_pwrdm" },
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
+ .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+ .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu0_54xx_clkdm = {
+ .name = "mpu0_clkdm",
+ .pwrdm = { .name = "cpu0_pwrdm" },
+ .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
+ .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
+ .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu1_54xx_clkdm = {
+ .name = "mpu1_clkdm",
+ .pwrdm = { .name = "cpu1_pwrdm" },
+ .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
+ .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
+ .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain coreaon_54xx_clkdm = {
+ .name = "coreaon_clkdm",
+ .pwrdm = { .name = "coreaon_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu_54xx_clkdm = {
+ .name = "mpu_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+ .wkdep_srcs = mpu_wkup_sleep_deps,
+ .sleepdep_srcs = mpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3init_54xx_clkdm = {
+ .name = "l3init_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+ .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
+ .wkdep_srcs = l3init_wkup_sleep_deps,
+ .sleepdep_srcs = l3init_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dma_54xx_clkdm = {
+ .name = "dma_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
+ .wkdep_srcs = dma_wkup_sleep_deps,
+ .sleepdep_srcs = dma_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_54xx_clkdm = {
+ .name = "l3instr_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain emif_54xx_clkdm = {
+ .name = "emif_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
+ .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_54xx_clkdm = {
+ .name = "emu_clkdm",
+ .pwrdm = { .name = "emu_pwrdm" },
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .cm_inst = OMAP54XX_PRM_EMU_CM_INST,
+ .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain cam_54xx_clkdm = {
+ .name = "cam_clkdm",
+ .pwrdm = { .name = "cam_pwrdm" },
+ .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
+ .cm_inst = OMAP54XX_CM_CORE_CAM_INST,
+ .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
+ .wkdep_srcs = cam_wkup_sleep_deps,
+ .sleepdep_srcs = cam_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_omap54xx[] __initdata = {
+ &l4sec_54xx_clkdm,
+ &iva_54xx_clkdm,
+ &mipiext_54xx_clkdm,
+ &l3main2_54xx_clkdm,
+ &l3main1_54xx_clkdm,
+ &custefuse_54xx_clkdm,
+ &ipu_54xx_clkdm,
+ &l4cfg_54xx_clkdm,
+ &abe_54xx_clkdm,
+ &dss_54xx_clkdm,
+ &dsp_54xx_clkdm,
+ &c2c_54xx_clkdm,
+ &l4per_54xx_clkdm,
+ &gpu_54xx_clkdm,
+ &wkupaon_54xx_clkdm,
+ &mpu0_54xx_clkdm,
+ &mpu1_54xx_clkdm,
+ &coreaon_54xx_clkdm,
+ &mpu_54xx_clkdm,
+ &l3init_54xx_clkdm,
+ &dma_54xx_clkdm,
+ &l3instr_54xx_clkdm,
+ &emif_54xx_clkdm,
+ &emu_54xx_clkdm,
+ &cam_54xx_clkdm,
+ NULL
+};
+
+void __init omap54xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&omap4_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_omap54xx);
+ clkdm_complete_init();
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 09/14] ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (5 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 08/14] ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 10/14] ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data Santosh Shilimkar
` (6 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Add the data file to describe all power domains inside the OMAP54XX soc.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
[santosh.shilimkar at ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/powerdomain.h | 1 +
arch/arm/mach-omap2/powerdomains54xx_data.c | 331 +++++++++++++++++++++++++++
2 files changed, 332 insertions(+)
create mode 100644 arch/arm/mach-omap2/powerdomains54xx_data.c
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c360..3d82f50 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
+extern void omap54xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 0000000..81f8a7c
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
+/*
+ * OMAP54XX Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare at ti.com)
+ * Benoit Cousson (b-cousson at ti.com)
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm_mpu54xx.h"
+
+/* core_54xx_pwrdm: CORE power domain */
+static struct powerdomain core_54xx_pwrdm = {
+ .name = "core_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_CORE_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 5,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* abe_54xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_54xx_pwrdm = {
+ .name = "abe_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_ABE_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_54xx_pwrdm = {
+ .name = "coreaon_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_COREAON_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+/* dss_54xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_54xx_pwrdm = {
+ .name = "dss_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_DSS_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_54xx_pwrdm = {
+ .name = "cpu0_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
+ .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu0_l1 */
+ },
+};
+
+/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_54xx_pwrdm = {
+ .name = "cpu1_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
+ .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu1_l1 */
+ },
+};
+
+/* emu_54xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_54xx_pwrdm = {
+ .name = "emu_pwrdm",
+ .voltdm = { .name = "wkup" },
+ .prcm_offs = OMAP54XX_PRM_EMU_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+};
+
+/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_54xx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = OMAP54XX_PRM_MPU_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_OFF_RET, /* mpu_ram */
+ },
+};
+
+/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_54xx_pwrdm = {
+ .name = "custefuse_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp_54xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp_54xx_pwrdm = {
+ .name = "dsp_pwrdm",
+ .voltdm = { .name = "mm" },
+ .prcm_offs = OMAP54XX_PRM_DSP_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dsp_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dsp_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_54xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_54xx_pwrdm = {
+ .name = "cam_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_CAM_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cam_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* cam_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
+static struct powerdomain l3init_54xx_pwrdm = {
+ .name = "l3init_pwrdm",
+ .voltdm = { .name = "core" },
+ .prcm_offs = OMAP54XX_PRM_L3INIT_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_54xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_54xx_pwrdm = {
+ .name = "gpu_pwrdm",
+ .voltdm = { .name = "mm" },
+ .prcm_offs = OMAP54XX_PRM_GPU_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_54xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_54xx_pwrdm = {
+ .name = "wkupaon_pwrdm",
+ .voltdm = { .name = "wkup" },
+ .prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* wkup_bank */
+ },
+};
+
+/* iva_54xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_54xx_pwrdm = {
+ .name = "iva_pwrdm",
+ .voltdm = { .name = "mm" },
+ .prcm_offs = OMAP54XX_PRM_IVA_INST,
+ .prcm_partition = OMAP54XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap54xx[] __initdata = {
+ &core_54xx_pwrdm,
+ &abe_54xx_pwrdm,
+ &coreaon_54xx_pwrdm,
+ &dss_54xx_pwrdm,
+ &cpu0_54xx_pwrdm,
+ &cpu1_54xx_pwrdm,
+ &emu_54xx_pwrdm,
+ &mpu_54xx_pwrdm,
+ &custefuse_54xx_pwrdm,
+ &dsp_54xx_pwrdm,
+ &cam_54xx_pwrdm,
+ &l3init_54xx_pwrdm,
+ &gpu_54xx_pwrdm,
+ &wkupaon_54xx_pwrdm,
+ &iva_54xx_pwrdm,
+ NULL
+};
+
+void __init omap54xx_powerdomains_init(void)
+{
+ pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_omap54xx);
+ pwrdm_complete_init();
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 10/14] ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (6 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 09/14] ARM: OMAP5: powerdomain " Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 11/14] ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data Santosh Shilimkar
` (5 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Adding the hwmod data for OMAP54xx SOCs.
Additional changes done on top of initial SOC data files.
- The IO resource information like dma request lines, irq number and
ocp address space can be populated via dt blob. So such data is stripped
from OMAP5 SOC hwmod data file.
- SDMA IO resource information is still kept since dmaengine work
is till ongoing. Once the legacy dma platform driver becomes obsolete,
SDMA io space information can be removed.
- The devices like dss, aess, usb which are missing the device tree bindings,
hwmod data is not added since OMAP5 is DT only build. When such devices add
the dt bindings, respective hwmod data can be added along with it.
With above update, we now need about ~2000 loc vs ~6000 loc with previous
version of the patch for OMAP5 hwmod data file. Ofcourse with addition of
few more drivers it can go upto ~2400 loc which is still better than the
earlier version.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.h | 1 +
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2151 ++++++++++++++++++++++++++++
2 files changed, 2152 insertions(+)
create mode 100644 arch/arm/mach-omap2/omap_hwmod_54xx_data.c
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f5..aab33fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
+extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 0000000..a538692
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2151 @@
+/*
+ * Hardware modules present on the OMAP54xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all OMAP5 interrupts external to MPUSS */
+#define OMAP54XX_IRQ_GIC_START 32
+
+/* Base offset for all OMAP5 dma requests */
+#define OMAP54XX_DMA_REQ_START 1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
+ .name = "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod omap54xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &omap54xx_dmm_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod omap54xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &omap54xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap54xx_l3_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
+ .name = "l3_main_2",
+ .class = &omap54xx_l3_hwmod_class,
+ .clkdm_name = "l3main2_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l3_main_3 */
+static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
+ .name = "l3_main_3",
+ .class = &omap54xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_abe */
+static struct omap_hwmod omap54xx_l4_abe_hwmod = {
+ .name = "l4_abe",
+ .class = &omap54xx_l4_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_cfg */
+static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
+ .name = "l4_cfg",
+ .class = &omap54xx_l4_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l4_per */
+static struct omap_hwmod omap54xx_l4_per_hwmod = {
+ .name = "l4_per",
+ .class = &omap54xx_l4_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l4_wkup */
+static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &omap54xx_l4_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
+ .name = "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod omap54xx_mpu_private_hwmod = {
+ .name = "mpu_private",
+ .class = &omap54xx_mpu_bus_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
+ .name = "counter",
+ .sysc = &omap54xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap54xx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .class = &omap54xx_counter_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
+ .name = "dma",
+ .sysc = &omap54xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
+ { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
+ { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
+ { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
+ { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod omap54xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &omap54xx_dma_hwmod_class,
+ .clkdm_name = "dma_clkdm",
+ .mpu_irqs = omap54xx_dma_system_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
+};
+
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
+ .name = "dmic",
+ .sysc = &omap54xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap54xx_dmic_hwmod = {
+ .name = "dmic",
+ .class = &omap54xx_dmic_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "dmic_gfclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ * external memory interface no1 (wrapper)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &omap54xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod omap54xx_emif1_hwmod = {
+ .name = "emif1",
+ .class = &omap54xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .main_clk = "dpll_core_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* emif2 */
+static struct omap_hwmod omap54xx_emif2_hwmod = {
+ .name = "emif2",
+ .class = &omap54xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .main_clk = "dpll_core_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap54xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio5_hwmod = {
+ .name = "gpio5",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio6_hwmod = {
+ .name = "gpio6",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio7_hwmod = {
+ .name = "gpio7",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio7_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio8_hwmod = {
+ .name = "gpio8",
+ .class = &omap54xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio8_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &omap54xx_i2c_sysc,
+ .reset = &omap_i2c_reset,
+ .rev = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap54xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &omap54xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod omap54xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &omap54xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod omap54xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &omap54xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod omap54xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &omap54xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod omap54xx_i2c5_hwmod = {
+ .name = "i2c5",
+ .class = &omap54xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
+ .name = "kbd",
+ .sysc = &omap54xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap54xx_kbd_hwmod = {
+ .name = "kbd",
+ .class = &omap54xx_kbd_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
+ .sysc_offs = 0x008c,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
+ .name = "mcbsp",
+ .sysc = &omap54xx_mcbsp_sysc,
+ .rev = MCBSP_CONFIG_TYPE4,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+ { .role = "pad_fck", .clk = "pad_clks_ck" },
+ { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
+ .name = "mcbsp1",
+ .class = &omap54xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "mcbsp1_gfclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mcbsp1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+ { .role = "pad_fck", .clk = "pad_clks_ck" },
+ { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap54xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "mcbsp2_gfclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mcbsp2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+ { .role = "pad_fck", .clk = "pad_clks_ck" },
+ { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap54xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "mcbsp3_gfclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mcbsp3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
+ .name = "mcpdm",
+ .sysc = &omap54xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap54xx_mcpdm_hwmod = {
+ .name = "mcpdm",
+ .class = &omap54xx_mcpdm_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ /*
+ * It's suspected that the McPDM requires an off-chip main
+ * functional clock, controlled via I2C. This IP block is
+ * currently reset very early during boot, before I2C is
+ * available, so it doesn't seem that we have any choice in
+ * the kernel other than to avoid resetting it. XXX This is
+ * really a hardware issue workaround: every IP block should
+ * be able to source its main functional clock from either
+ * on-chip or off-chip sources. McPDM seems to be the only
+ * current exception.
+ */
+
+ .flags = HWMOD_EXT_OPT_MAIN_CLK,
+ .main_clk = "pad_clks_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &omap54xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap54xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &omap54xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &omap54xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &omap54xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+ .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap54xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &omap54xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &omap54xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+ { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap54xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &omap54xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "mmc1_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
+ .dev_attr = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod omap54xx_mmc2_hwmod = {
+ .name = "mmc2",
+ .class = &omap54xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "mmc2_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mmc3 */
+static struct omap_hwmod omap54xx_mmc3_hwmod = {
+ .name = "mmc3",
+ .class = &omap54xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mmc4 */
+static struct omap_hwmod omap54xx_mmc4_hwmod = {
+ .name = "mmc4",
+ .class = &omap54xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mmc5 */
+static struct omap_hwmod omap54xx_mmc5_hwmod = {
+ .name = "mmc5",
+ .class = &omap54xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod omap54xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &omap54xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+ .clockact = CLOCKACT_TEST_ICLK,
+};
+
+static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap54xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap54xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap54xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap54xx_timer_1ms_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "timer1_gfclk_mux",
+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer2 */
+static struct omap_hwmod omap54xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &omap54xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer2_gfclk_mux",
+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer3 */
+static struct omap_hwmod omap54xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer3_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer4 */
+static struct omap_hwmod omap54xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer4_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer5 */
+static struct omap_hwmod omap54xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "timer5_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer6 */
+static struct omap_hwmod omap54xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "timer6_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer7 */
+static struct omap_hwmod omap54xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "timer7_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer8 */
+static struct omap_hwmod omap54xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .main_clk = "timer8_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer9 */
+static struct omap_hwmod omap54xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer9_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer10 */
+static struct omap_hwmod omap54xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &omap54xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer10_gfclk_mux",
+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer11 */
+static struct omap_hwmod omap54xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &omap54xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "timer11_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
+ .rev_offs = 0x0050,
+ .sysc_offs = 0x0054,
+ .syss_offs = 0x0058,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
+ .name = "uart",
+ .sysc = &omap54xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap54xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart2 */
+static struct omap_hwmod omap54xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod omap54xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart4 */
+static struct omap_hwmod omap54xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart5 */
+static struct omap_hwmod omap54xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart6 */
+static struct omap_hwmod omap54xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &omap54xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg_ss' class
+ * 2.0 super speed (usb_otg_ss) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
+ .name = "usb_otg_ss",
+ .sysc = &omap54xx_usb_otg_ss_sysc,
+};
+
+/* usb_otg_ss */
+static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
+ { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
+};
+
+static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
+ .name = "usb_otg_ss",
+ .class = &omap54xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_ss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &omap54xx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &omap54xx_wd_timer_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_dmm_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
+ .master = &omap54xx_l3_main_3_hwmod,
+ .slave = &omap54xx_l3_instr_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
+ .master = &omap54xx_l3_main_2_hwmod,
+ .slave = &omap54xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
+ .master = &omap54xx_mpu_hwmod,
+ .slave = &omap54xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_l3_main_3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
+ .master = &omap54xx_l3_main_2_hwmod,
+ .slave = &omap54xx_l3_main_3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_l3_main_3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_l4_abe_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
+ .master = &omap54xx_mpu_hwmod,
+ .slave = &omap54xx_l4_abe_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_l4_cfg_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
+ .master = &omap54xx_l3_main_2_hwmod,
+ .slave = &omap54xx_l4_per_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
+ .master = &omap54xx_l3_main_1_hwmod,
+ .slave = &omap54xx_l4_wkup_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
+ .master = &omap54xx_mpu_hwmod,
+ .slave = &omap54xx_mpu_private_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
+ .master = &omap54xx_l4_wkup_hwmod,
+ .slave = &omap54xx_counter_32k_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x4a056000,
+ .pa_end = 0x4a056fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_dma_system_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = omap54xx_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_dmic_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
+ .master = &omap54xx_mpu_hwmod,
+ .slave = &omap54xx_emif1_hwmod,
+ .clk = "dpll_core_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
+ .master = &omap54xx_mpu_hwmod,
+ .slave = &omap54xx_emif2_hwmod,
+ .clk = "dpll_core_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
+ .master = &omap54xx_l4_wkup_hwmod,
+ .slave = &omap54xx_gpio1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio6_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio7_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_gpio8_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_i2c1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_i2c2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_i2c3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_i2c4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_i2c5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
+ .master = &omap54xx_l4_wkup_hwmod,
+ .slave = &omap54xx_kbd_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_mcbsp1_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_mcbsp2_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_mcbsp3_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_mcpdm_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mcspi1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mcspi2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mcspi3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mcspi4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mmc1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mmc2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mmc3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mmc4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_mmc5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_mpu_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
+ .master = &omap54xx_l4_wkup_hwmod,
+ .slave = &omap54xx_timer1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_timer5_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_timer6_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_timer7_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
+ .master = &omap54xx_l4_abe_hwmod,
+ .slave = &omap54xx_timer8_hwmod,
+ .clk = "abe_iclk",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer9_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer10_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_timer11_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
+ .master = &omap54xx_l4_per_hwmod,
+ .slave = &omap54xx_uart6_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> usb_otg_ss */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_usb_otg_ss_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
+ .master = &omap54xx_l4_wkup_hwmod,
+ .slave = &omap54xx_wd_timer2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
+ &omap54xx_l3_main_1__dmm,
+ &omap54xx_l3_main_3__l3_instr,
+ &omap54xx_l3_main_2__l3_main_1,
+ &omap54xx_l4_cfg__l3_main_1,
+ &omap54xx_mpu__l3_main_1,
+ &omap54xx_l3_main_1__l3_main_2,
+ &omap54xx_l4_cfg__l3_main_2,
+ &omap54xx_l3_main_1__l3_main_3,
+ &omap54xx_l3_main_2__l3_main_3,
+ &omap54xx_l4_cfg__l3_main_3,
+ &omap54xx_l3_main_1__l4_abe,
+ &omap54xx_mpu__l4_abe,
+ &omap54xx_l3_main_1__l4_cfg,
+ &omap54xx_l3_main_2__l4_per,
+ &omap54xx_l3_main_1__l4_wkup,
+ &omap54xx_mpu__mpu_private,
+ &omap54xx_l4_wkup__counter_32k,
+ &omap54xx_l4_cfg__dma_system,
+ &omap54xx_l4_abe__dmic,
+ &omap54xx_mpu__emif1,
+ &omap54xx_mpu__emif2,
+ &omap54xx_l4_wkup__gpio1,
+ &omap54xx_l4_per__gpio2,
+ &omap54xx_l4_per__gpio3,
+ &omap54xx_l4_per__gpio4,
+ &omap54xx_l4_per__gpio5,
+ &omap54xx_l4_per__gpio6,
+ &omap54xx_l4_per__gpio7,
+ &omap54xx_l4_per__gpio8,
+ &omap54xx_l4_per__i2c1,
+ &omap54xx_l4_per__i2c2,
+ &omap54xx_l4_per__i2c3,
+ &omap54xx_l4_per__i2c4,
+ &omap54xx_l4_per__i2c5,
+ &omap54xx_l4_wkup__kbd,
+ &omap54xx_l4_abe__mcbsp1,
+ &omap54xx_l4_abe__mcbsp2,
+ &omap54xx_l4_abe__mcbsp3,
+ &omap54xx_l4_abe__mcpdm,
+ &omap54xx_l4_per__mcspi1,
+ &omap54xx_l4_per__mcspi2,
+ &omap54xx_l4_per__mcspi3,
+ &omap54xx_l4_per__mcspi4,
+ &omap54xx_l4_per__mmc1,
+ &omap54xx_l4_per__mmc2,
+ &omap54xx_l4_per__mmc3,
+ &omap54xx_l4_per__mmc4,
+ &omap54xx_l4_per__mmc5,
+ &omap54xx_l4_cfg__mpu,
+ &omap54xx_l4_wkup__timer1,
+ &omap54xx_l4_per__timer2,
+ &omap54xx_l4_per__timer3,
+ &omap54xx_l4_per__timer4,
+ &omap54xx_l4_abe__timer5,
+ &omap54xx_l4_abe__timer6,
+ &omap54xx_l4_abe__timer7,
+ &omap54xx_l4_abe__timer8,
+ &omap54xx_l4_per__timer9,
+ &omap54xx_l4_per__timer10,
+ &omap54xx_l4_per__timer11,
+ &omap54xx_l4_per__uart1,
+ &omap54xx_l4_per__uart2,
+ &omap54xx_l4_per__uart3,
+ &omap54xx_l4_per__uart4,
+ &omap54xx_l4_per__uart5,
+ &omap54xx_l4_per__uart6,
+ &omap54xx_l4_cfg__usb_otg_ss,
+ &omap54xx_l4_wkup__wd_timer2,
+ NULL,
+};
+
+int __init omap54xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 11/14] ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (7 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 10/14] ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 12/14] ARM: OMAP5: Enable build and frameowrk initialisations Santosh Shilimkar
` (4 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
Add voltagedomain related data for OMAP54XX SOCs. OMAP4 OPP data is
used for now. OMAP5 OPP data will be added as part of OMAP5 DVFS
support.
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/voltage.h | 1 +
arch/arm/mach-omap2/voltagedomains54xx_data.c | 102 +++++++++++++++++++++++++
2 files changed, 103 insertions(+)
create mode 100644 arch/arm/mach-omap2/voltagedomains54xx_data.c
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f1..5998eed 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void);
extern void am33xx_voltagedomains_init(void);
extern void omap44xx_voltagedomains_init(void);
+extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 0000000..72b8971
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,102 @@
+/*
+ * OMAP5 Voltage Management Routines
+ *
+ * Based on voltagedomains44xx_data.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include "common.h"
+
+#include "prm54xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+
+static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
+ .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
+ .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
+ .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+
+static struct voltagedomain omap5_voltdm_mpu = {
+ .name = "mpu",
+ .scalable = true,
+ .read = omap4_prm_vcvp_read,
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_mpu,
+ .vfsm = &omap5_vdd_mpu_vfsm,
+ .vp = &omap4_vp_mpu,
+};
+
+static struct voltagedomain omap5_voltdm_mm = {
+ .name = "mm",
+ .scalable = true,
+ .read = omap4_prm_vcvp_read,
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_iva,
+ .vfsm = &omap5_vdd_mm_vfsm,
+ .vp = &omap4_vp_iva,
+};
+
+static struct voltagedomain omap5_voltdm_core = {
+ .name = "core",
+ .scalable = true,
+ .read = omap4_prm_vcvp_read,
+ .write = omap4_prm_vcvp_write,
+ .rmw = omap4_prm_vcvp_rmw,
+ .vc = &omap4_vc_core,
+ .vfsm = &omap5_vdd_core_vfsm,
+ .vp = &omap4_vp_core,
+};
+
+static struct voltagedomain omap5_voltdm_wkup = {
+ .name = "wkup",
+};
+
+static struct voltagedomain *voltagedomains_omap5[] __initdata = {
+ &omap5_voltdm_mpu,
+ &omap5_voltdm_mm,
+ &omap5_voltdm_core,
+ &omap5_voltdm_wkup,
+ NULL,
+};
+
+static const char *sys_clk_name __initdata = "sys_clkin";
+
+void __init omap54xx_voltagedomains_init(void)
+{
+ struct voltagedomain *voltdm;
+ int i;
+
+ /*
+ * XXX Will depend on the process, validation, and binning
+ * for the currently-running IC. Use OMAP4 data for time being.
+ */
+#ifdef CONFIG_PM_OPP
+ omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
+ omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
+ omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
+#endif
+
+ for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
+ voltdm->sys_clk.name = sys_clk_name;
+
+ voltdm_init(voltagedomains_omap5);
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 12/14] ARM: OMAP5: Enable build and frameowrk initialisations
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (8 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 11/14] ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up Santosh Shilimkar
` (3 subsequent siblings)
13 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
Include the OMAP5 data files in build. Initialise the voltage, power,
clock domains.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/Makefile | 4 ++++
arch/arm/mach-omap2/io.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d67..27448ab 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
+obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@@ -141,6 +142,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@@ -156,6 +158,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -198,6 +201,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
+obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99..a0cc2bb 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -631,7 +631,14 @@ void __init omap5_init_early(void)
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap_prm_base_init();
omap_cm_base_init();
+ omap44xx_prm_init();
omap5xxx_check_revision();
+ omap54xx_voltagedomains_init();
+ omap54xx_powerdomains_init();
+ omap54xx_clockdomains_init();
+ omap54xx_hwmod_init();
+ omap_hwmod_init_postsetup();
+
}
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (9 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 12/14] ARM: OMAP5: Enable build and frameowrk initialisations Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-06-06 4:00 ` Paul Walmsley
2013-05-29 16:38 ` [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file Santosh Shilimkar
` (2 subsequent siblings)
13 siblings, 1 reply; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Vaibhav Hiremath <hvaibhav@ti.com>
AM33XX only supports DT boot mode and with addition of
extracting module resources like, irq, dma and address space
from DT block, so now we can remove duplicate information from
hwmod data file.
This patch cleanups-up/deletes,
- All references to "omap_hwmod_irq_info" data.
- All references to "omap_hwmod_dma_info" data.
- References to "omap_hwmod_addr_space" of the modules
for which DT node is available with required address
space information.
- For the modules where "sysc" field is not applicable,
we don't need module address space, so remove them as well.
- The hwmod like firewall etc which are not useful are also
deleted.
This cleanup gets us around ~1100 LOC of negative diff.
Patch is boot tested on AM335x-EVM along with below modules -
- Matrix-keypad
- Volume up/down keys
- Ethernet
- RTC
- WDT
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1067 ----------------------------
1 file changed, 1067 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc..3c7675a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
*/
/*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
- .name = "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod am33xx_emif_fw_hwmod = {
- .name = "emif_fw",
- .class = &am33xx_emif_fw_hwmod_class,
- .clkdm_name = "l4fw_clkdm",
- .main_clk = "l4fw_gclk",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'emif' class
* instance(s): emif
*/
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
.sysc = &am33xx_emif_sysc,
};
-static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
- { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
.name = "emif",
.class = &am33xx_emif_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .mpu_irqs = am33xx_emif_irqs,
.main_clk = "dpll_ddr_m2_div2_ck",
.prcm = {
.omap4 = {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
.name = "l3",
};
-/* l3_main (l3_fast) */
-static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
- { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
- { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_l3_main_hwmod = {
.name = "l3_main",
.class = &am33xx_l3_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .mpu_irqs = am33xx_l3_main_irqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
},
};
-/* l4_fw */
-static struct omap_hwmod am33xx_l4_fw_hwmod = {
- .name = "l4_fw",
- .class = &am33xx_l4_hwmod_class,
- .clkdm_name = "l4fw_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
/*
* 'mpu' class
*/
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
.name = "mpu",
};
-/* mpu */
-static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
- { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
- { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
- { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
- { .name = "bench", .irq = 3 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_mpu_hwmod = {
.name = "mpu",
.class = &am33xx_mpu_hwmod_class,
.clkdm_name = "mpu_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .mpu_irqs = am33xx_mpu_irqs,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};
-static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
- { .name = "txev", .irq = 78 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
/* wkup_m3 */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
- .mpu_irqs = am33xx_wkup_m3_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
{ .name = "pruss", .rst_shift = 1 },
};
-static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
- { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
- { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
- { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
- { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
- { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
- { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
- { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
- { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
/* pru-icss */
/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod am33xx_pruss_hwmod = {
.name = "pruss",
.class = &am33xx_pruss_hwmod_class,
.clkdm_name = "pruss_ocp_clkdm",
- .mpu_irqs = am33xx_pruss_irqs,
.main_clk = "pruss_ocp_gclk",
.prcm = {
.omap4 = {
@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
{ .name = "gfx", .rst_shift = 0 },
};
-static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
- { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_gfx_hwmod = {
.name = "gfx",
.class = &am33xx_gfx_hwmod_class,
.clkdm_name = "gfx_l3_clkdm",
- .mpu_irqs = am33xx_gfx_irqs,
.main_clk = "gfx_fck_div_ck",
.prcm = {
.omap4 = {
@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
.sysc = &am33xx_adc_tsc_sysc,
};
-static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
- { .irq = 16 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = am33xx_adc_tsc_irqs,
.main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
.sysc = &am33xx_aes0_sysc,
};
-static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
- { .irq = 103 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
- { .name = "tx", .dma_req = 6, },
- { .name = "rx", .dma_req = 5, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_aes0_hwmod = {
.name = "aes",
.class = &am33xx_aes0_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_aes0_irqs,
- .sdma_reqs = am33xx_aes0_edma_reqs,
.main_clk = "aes0_fck",
.prcm = {
.omap4 = {
@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
.sysc = &am33xx_sha0_sysc,
};
-static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
- { .irq = 109 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
- { .name = "rx", .dma_req = 36, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_sha0_hwmod = {
.name = "sham",
.class = &am33xx_sha0_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_sha0_irqs,
- .sdma_reqs = am33xx_sha0_edma_reqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
};
/* smartreflex0 */
-static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
- { .irq = 120 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_smartreflex0_hwmod = {
.name = "smartreflex0",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = am33xx_smartreflex0_irqs,
.main_clk = "smartreflex0_fck",
.prcm = {
.omap4 = {
@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
};
/* smartreflex1 */
-static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
- { .irq = 121 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_smartreflex1_hwmod = {
.name = "smartreflex1",
.class = &am33xx_smartreflex_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = am33xx_smartreflex1_irqs,
.main_clk = "smartreflex1_fck",
.prcm = {
.omap4 = {
@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control",
};
-static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
- { .irq = 8 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_control_hwmod = {
.name = "control",
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .mpu_irqs = am33xx_control_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.sysc = &am33xx_cpgmac_sysc,
};
-static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
- { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
- { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
- { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
- { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .mpu_irqs = am33xx_cpgmac0_irqs,
.main_clk = "cpsw_125mhz_gclk",
.prcm = {
.omap4 = {
@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
};
/* dcan0 */
-static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
- { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
- { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_dcan0_hwmod = {
.name = "d_can0",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_dcan0_irqs,
.main_clk = "dcan0_fck",
.prcm = {
.omap4 = {
@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
};
/* dcan1 */
-static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
- { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
- { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
- { .irq = -1 },
-};
static struct omap_hwmod am33xx_dcan1_hwmod = {
.name = "d_can1",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_dcan1_irqs,
.main_clk = "dcan1_fck",
.prcm = {
.omap4 = {
@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
.sysc = &am33xx_elm_sysc,
};
-static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
- { .irq = 4 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_elm_hwmod = {
.name = "elm",
.class = &am33xx_elm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_elm_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
};
/* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
- { .irq = 31 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ecap0_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep0 */
-static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
- { .irq = 79 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_eqep0_hwmod = {
.name = "eqep0",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_eqep0_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
- { .name = "int", .irq = 86 + OMAP_INTC_START, },
- { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk",
};
@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
};
/* ecap1 */
-static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
- { .irq = 47 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ecap1_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep1 */
-static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
- { .irq = 88 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_eqep1_hwmod = {
.name = "eqep1",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_eqep1_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm1 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
- { .name = "int", .irq = 87 + OMAP_INTC_START, },
- { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
};
@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
};
/* ecap2 */
-static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
- { .irq = 61 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2",
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ecap2_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep2 */
-static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
- { .irq = 89 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_eqep2_hwmod = {
.name = "eqep2",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_eqep2_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm2 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
- { .name = "int", .irq = 39 + OMAP_INTC_START, },
- { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk",
};
@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio0_dbclk" },
};
-static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
- { .irq = 96 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_gpio0_hwmod = {
.name = "gpio1",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = am33xx_gpio0_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
};
/* gpio1 */
-static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
- { .irq = 98 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = am33xx_gpio1_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
};
/* gpio2 */
-static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
- { .irq = 32 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = am33xx_gpio2_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
};
/* gpio3 */
-static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
- { .irq = 62 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = am33xx_gpio3_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
.sysc = &gpmc_sysc,
};
-static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
- { .irq = 100 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_gpmc_hwmod = {
.name = "gpmc",
.class = &am33xx_gpmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
- .mpu_irqs = am33xx_gpmc_irqs,
.main_clk = "l3s_gclk",
.prcm = {
.omap4 = {
@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
};
/* i2c1 */
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
- { .irq = 70 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
- { .name = "tx", .dma_req = 0, },
- { .name = "rx", .dma_req = 0, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_i2c1_hwmod = {
.name = "i2c1",
.class = &i2c_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = i2c1_mpu_irqs,
- .sdma_reqs = i2c1_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
};
/* i2c1 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
- { .irq = 71 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
- { .name = "tx", .dma_req = 0, },
- { .name = "rx", .dma_req = 0, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_i2c2_hwmod = {
.name = "i2c2",
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = i2c2_mpu_irqs,
- .sdma_reqs = i2c2_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
};
/* i2c3 */
-static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
- { .name = "tx", .dma_req = 0, },
- { .name = "rx", .dma_req = 0, },
- { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
- { .irq = 30 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_i2c3_hwmod = {
.name = "i2c3",
.class = &i2c_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = i2c3_mpu_irqs,
- .sdma_reqs = i2c3_edma_reqs,
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
.sysc = &lcdc_sysc,
};
-static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
- { .irq = 36 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_lcdc_hwmod = {
.name = "lcdc",
.class = &am33xx_lcdc_hwmod_class,
.clkdm_name = "lcdc_clkdm",
- .mpu_irqs = am33xx_lcdc_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "lcd_gclk",
.prcm = {
@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
.sysc = &am33xx_mailbox_sysc,
};
-static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
- { .irq = 77 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_mailbox_hwmod = {
.name = "mailbox",
.class = &am33xx_mailbox_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_mailbox_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
};
/* mcasp0 */
-static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
- { .name = "ax", .irq = 80 + OMAP_INTC_START, },
- { .name = "ar", .irq = 81 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
- { .name = "tx", .dma_req = 8, },
- { .name = "rx", .dma_req = 9, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_mcasp0_hwmod = {
.name = "mcasp0",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
- .mpu_irqs = am33xx_mcasp0_irqs,
- .sdma_reqs = am33xx_mcasp0_edma_reqs,
.main_clk = "mcasp0_fck",
.prcm = {
.omap4 = {
@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
};
/* mcasp1 */
-static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
- { .name = "ax", .irq = 82 + OMAP_INTC_START, },
- { .name = "ar", .irq = 83 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
- { .name = "tx", .dma_req = 10, },
- { .name = "rx", .dma_req = 11, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_mcasp1_hwmod = {
.name = "mcasp1",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
- .mpu_irqs = am33xx_mcasp1_irqs,
- .sdma_reqs = am33xx_mcasp1_edma_reqs,
.main_clk = "mcasp1_fck",
.prcm = {
.omap4 = {
@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
};
/* mmc0 */
-static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
- { .irq = 64 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
- { .name = "tx", .dma_req = 24, },
- { .name = "rx", .dma_req = 25, },
- { .dma_req = -1 }
-};
-
static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
.name = "mmc1",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_mmc0_irqs,
- .sdma_reqs = am33xx_mmc0_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
};
/* mmc1 */
-static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
- { .irq = 28 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
- { .name = "tx", .dma_req = 2, },
- { .name = "rx", .dma_req = 3, },
- { .dma_req = -1 }
-};
-
static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
.name = "mmc2",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_mmc1_irqs,
- .sdma_reqs = am33xx_mmc1_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
};
/* mmc2 */
-static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
- { .irq = 29 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
- { .name = "tx", .dma_req = 64, },
- { .name = "rx", .dma_req = 65, },
- { .dma_req = -1 }
-};
-
static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};
@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
.name = "mmc3",
.class = &am33xx_mmc_hwmod_class,
.clkdm_name = "l3s_clkdm",
- .mpu_irqs = am33xx_mmc2_irqs,
- .sdma_reqs = am33xx_mmc2_edma_reqs,
.main_clk = "mmc_clk",
.prcm = {
.omap4 = {
@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
.sysc = &am33xx_rtc_sysc,
};
-static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
- { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
- { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_rtc_hwmod = {
.name = "rtc",
.class = &am33xx_rtc_hwmod_class,
.clkdm_name = "l4_rtc_clkdm",
- .mpu_irqs = am33xx_rtc_irqs,
.main_clk = "clk_32768_ck",
.prcm = {
.omap4 = {
@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
};
/* spi0 */
-static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
- { .irq = 65 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
- { .name = "rx0", .dma_req = 17 },
- { .name = "tx0", .dma_req = 16 },
- { .name = "rx1", .dma_req = 19 },
- { .name = "tx1", .dma_req = 18 },
- { .dma_req = -1 }
-};
-
static struct omap2_mcspi_dev_attr mcspi_attrib = {
.num_chipselect = 2,
};
@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
.name = "spi0",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_spi0_irqs,
- .sdma_reqs = am33xx_mcspi0_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
};
/* spi1 */
-static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
- { .irq = 125 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
- { .name = "rx0", .dma_req = 43 },
- { .name = "tx0", .dma_req = 42 },
- { .name = "rx1", .dma_req = 45 },
- { .name = "tx1", .dma_req = 44 },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod am33xx_spi1_hwmod = {
.name = "spi1",
.class = &am33xx_spi_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_spi1_irqs,
- .sdma_reqs = am33xx_mcspi1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
.sysc = &am33xx_timer1ms_sysc,
};
-static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
- { .irq = 67 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer1_hwmod = {
.name = "timer1",
.class = &am33xx_timer1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = am33xx_timer1_irqs,
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
- { .irq = 68 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer2_hwmod = {
.name = "timer2",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer2_irqs,
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
- { .irq = 69 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer3_hwmod = {
.name = "timer3",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer3_irqs,
.main_clk = "timer3_fck",
.prcm = {
.omap4 = {
@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
- { .irq = 92 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer4_hwmod = {
.name = "timer4",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer4_irqs,
.main_clk = "timer4_fck",
.prcm = {
.omap4 = {
@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
- { .irq = 93 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer5_hwmod = {
.name = "timer5",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer5_irqs,
.main_clk = "timer5_fck",
.prcm = {
.omap4 = {
@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
- { .irq = 94 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer6_hwmod = {
.name = "timer6",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer6_irqs,
.main_clk = "timer6_fck",
.prcm = {
.omap4 = {
@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
- { .irq = 95 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_timer7_hwmod = {
.name = "timer7",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_timer7_irqs,
.main_clk = "timer7_fck",
.prcm = {
.omap4 = {
@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
.name = "tpcc",
};
-static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
- { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
- { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
- { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_tpcc_hwmod = {
.name = "tpcc",
.class = &am33xx_tpcc_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_tpcc_irqs,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
};
/* tptc0 */
-static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
- { .irq = 112 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_tptc0_hwmod = {
.name = "tptc0",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_tptc0_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk",
.prcm = {
@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
};
/* tptc1 */
-static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
- { .irq = 113 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_tptc1_hwmod = {
.name = "tptc1",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_tptc1_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
};
/* tptc2 */
-static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
- { .irq = 114 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_tptc2_hwmod = {
.name = "tptc2",
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
- .mpu_irqs = am33xx_tptc2_irqs,
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "l3_gclk",
.prcm = {
@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = {
};
/* uart1 */
-static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
- { .name = "tx", .dma_req = 26, },
- { .name = "rx", .dma_req = 27, },
- { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
- { .irq = 72 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart1_hwmod = {
.name = "uart1",
.class = &uart_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart1_irqs,
- .sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
.prcm = {
.omap4 = {
@@ -2007,18 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
- { .irq = 73 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart2_hwmod = {
.name = "uart2",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart2_irqs,
- .sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -2029,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
};
/* uart3 */
-static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
- { .name = "tx", .dma_req = 30, },
- { .name = "rx", .dma_req = 31, },
- { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
- { .irq = 74 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart3_hwmod = {
.name = "uart3",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart3_irqs,
- .sdma_reqs = uart3_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -2056,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
- { .irq = 44 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart4_hwmod = {
.name = "uart4",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart4_irqs,
- .sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -2077,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
- { .irq = 45 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart5_hwmod = {
.name = "uart5",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart5_irqs,
- .sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -2098,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
},
};
-static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
- { .irq = 46 + OMAP_INTC_START, },
- { .irq = -1 },
-};
-
static struct omap_hwmod am33xx_uart6_hwmod = {
.name = "uart6",
.class = &uart_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = am33xx_uart6_irqs,
- .sdma_reqs = uart1_edma_reqs,
.main_clk = "dpll_per_m2_div4_ck",
.prcm = {
.omap4 = {
@@ -2173,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
.sysc = &am33xx_usbhsotg_sysc,
};
-static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
- { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
- { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
- { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
- { .irq = -1, },
-};
-
static struct omap_hwmod am33xx_usbss_hwmod = {
.name = "usb_otg_hs",
.class = &am33xx_usbotg_class,
.clkdm_name = "l3s_clkdm",
- .mpu_irqs = am33xx_usbss_mpu_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "usbotg_fck",
.prcm = {
@@ -2200,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
* Interfaces
*/
-/* l4 fw -> emif fw */
-static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
- .master = &am33xx_l4_fw_hwmod,
- .slave = &am33xx_emif_fw_hwmod,
- .clk = "l4fw_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
{
.pa_start = 0x4c000000,
@@ -2265,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3 s -> l4 fw */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am33xx_l4_fw_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3 main -> l3 instr */
static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
.master = &am33xx_l3_main_hwmod,
@@ -2322,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
};
/* l4 wkup -> wkup m3 */
-static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
- {
- .name = "umem",
- .pa_start = 0x44d00000,
- .pa_end = 0x44d00000 + SZ_16K - 1,
- .flags = ADDR_TYPE_RT
- },
- {
- .name = "dmem",
- .pa_start = 0x44d80000,
- .pa_end = 0x44d80000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wkup_m3_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_wkup_m3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 hs -> pru-icss */
-static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
- {
- .pa_start = 0x4a300000,
- .pa_end = 0x4a300000 + SZ_512K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_pruss_hwmod,
.clk = "dpll_core_m4_ck",
- .addr = am33xx_pruss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> gfx */
-static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
- {
- .pa_start = 0x56000000,
- .pa_end = 0x56000000 + SZ_16M - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_gfx_hwmod,
.clk = "dpll_core_m4_ck",
- .addr = am33xx_gfx_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 wkup -> smartreflex0 */
-static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
- {
- .pa_start = 0x44e37000,
- .pa_end = 0x44e37000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_smartreflex0_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> smartreflex1 */
-static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
- {
- .pa_start = 0x44e39000,
- .pa_end = 0x44e39000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex1_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_smartreflex1_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> control */
-static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
- {
- .pa_start = 0x44e10000,
- .pa_end = 0x44e10000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_control_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_control_addrs,
.user = OCP_USER_MPU,
};
/* l4 wkup -> rtc */
-static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
- {
- .pa_start = 0x44e3e000,
- .pa_end = 0x44e3e000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_rtc_hwmod,
.clk = "clkdiv32k_ick",
- .addr = am33xx_rtc_addrs,
.user = OCP_USER_MPU,
};
/* l4 per/ls -> DCAN0 */
-static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
- {
- .pa_start = 0x481CC000,
- .pa_end = 0x481CC000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan0_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_dcan0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> DCAN1 */
-static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
- {
- .pa_start = 0x481D0000,
- .pa_end = 0x481D0000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_dcan1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> GPIO2 */
-static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
- {
- .pa_start = 0x4804C000,
- .pa_end = 0x4804C000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> gpio3 */
-static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
- {
- .pa_start = 0x481AC000,
- .pa_end = 0x481AC000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> gpio4 */
-static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
- {
- .pa_start = 0x481AE000,
- .pa_end = 0x481AE000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_gpio3_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 WKUP -> I2C1 */
-static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
- {
- .pa_start = 0x44E0B000,
- .pa_end = 0x44E0B000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_i2c1_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_i2c1_addr_space,
.user = OCP_USER_MPU,
};
/* L4 WKUP -> GPIO1 */
-static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
- {
- .pa_start = 0x44E07000,
- .pa_end = 0x44E07000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_gpio0_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_gpio0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2598,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
- /* cpsw ss */
- {
- .pa_start = 0x4a100000,
- .pa_end = 0x4a100000 + SZ_2K - 1,
- },
- /* cpsw wr */
- {
- .pa_start = 0x4a101200,
- .pa_end = 0x4a101200 + SZ_256 - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
- .addr = am33xx_cpgmac0_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
- {
- .pa_start = 0x4A101000,
- .pa_end = 0x4A101000 + SZ_256 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod,
- .addr = am33xx_mdio_addr_space,
.user = OCP_USER_MPU,
};
@@ -2670,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
- {
- .pa_start = 0x48300100,
- .pa_end = 0x48300100 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ecap0_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ecap0_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
- {
- .pa_start = 0x48300180,
- .pa_end = 0x48300180 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_eqep0_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_eqep0_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
- {
- .pa_start = 0x48300200,
- .pa_end = 0x48300200 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ehrpwm0_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU,
};
@@ -2736,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
- {
- .pa_start = 0x48302100,
- .pa_end = 0x48302100 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ecap1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ecap1_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
- {
- .pa_start = 0x48302180,
- .pa_end = 0x48302180 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_eqep1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_eqep1_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
- {
- .pa_start = 0x48302200,
- .pa_end = 0x48302200 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
@@ -2801,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
- {
- .pa_start = 0x48304100,
- .pa_end = 0x48304100 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ecap2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
- {
- .pa_start = 0x48304180,
- .pa_end = 0x48304180 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_eqep2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_eqep2_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
- {
- .pa_start = 0x48304200,
- .pa_end = 0x48304200 + SZ_128 - 1,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
@@ -2868,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
};
/* i2c2 */
-static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
- {
- .pa_start = 0x4802A000,
- .pa_end = 0x4802A000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_i2c2_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
- {
- .pa_start = 0x4819C000,
- .pa_end = 0x4819C000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_i2c3_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_i2c3_addr_space,
.user = OCP_USER_MPU,
};
@@ -2938,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
};
/* l4 ls -> spinlock */
-static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
- {
- .pa_start = 0x480Ca000,
- .pa_end = 0x480Ca000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spinlock_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_spinlock_addrs,
.user = OCP_USER_MPU,
};
@@ -2973,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
.user = OCP_USER_MPU,
};
-/* l3 s -> mcasp0 data */
-static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
- {
- .pa_start = 0x46000000,
- .pa_end = 0x46000000 + SZ_4M - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am33xx_mcasp0_hwmod,
- .clk = "l3s_gclk",
- .addr = am33xx_mcasp0_data_addr_space,
- .user = OCP_USER_SDMA,
-};
-
/* l4 ls -> mcasp1 */
static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
{
@@ -3009,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
.user = OCP_USER_MPU,
};
-/* l3 s -> mcasp1 data */
-static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
- {
- .pa_start = 0x46400000,
- .pa_end = 0x46400000 + SZ_4M - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am33xx_mcasp1_hwmod,
- .clk = "l3s_gclk",
- .addr = am33xx_mcasp1_data_addr_space,
- .user = OCP_USER_SDMA,
-};
-
/* l4 ls -> mmc0 */
static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
{
@@ -3082,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
};
/* l4 ls -> mcspi0 */
-static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
- {
- .pa_start = 0x48030000,
- .pa_end = 0x48030000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi0_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_mcspi0_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> mcspi1 */
-static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
- {
- .pa_start = 0x481A0000,
- .pa_end = 0x481A0000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi1_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_mcspi1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 wkup -> timer1 */
-static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
- {
- .pa_start = 0x44E31000,
- .pa_end = 0x44E31000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_timer1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer2 */
-static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
- {
- .pa_start = 0x48040000,
- .pa_end = 0x48040000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer2_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer3 */
-static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
- {
- .pa_start = 0x48042000,
- .pa_end = 0x48042000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer3_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer3_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer4 */
-static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
- {
- .pa_start = 0x48044000,
- .pa_end = 0x48044000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer4_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer4_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer5 */
-static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
- {
- .pa_start = 0x48046000,
- .pa_end = 0x48046000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer5_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer5_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer6 */
-static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
- {
- .pa_start = 0x48048000,
- .pa_end = 0x48048000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer6_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer6_addr_space,
.user = OCP_USER_MPU,
};
/* l4 per -> timer7 */
-static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
- {
- .pa_start = 0x4804A000,
- .pa_end = 0x4804A000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer7_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_timer7_addr_space,
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc */
-static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
- {
- .pa_start = 0x49000000,
- .pa_end = 0x49000000 + SZ_32K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_tpcc_hwmod,
.clk = "l3_gclk",
- .addr = am33xx_tpcc_addr_space,
.user = OCP_USER_MPU,
};
@@ -3316,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
};
/* l4 wkup -> uart1 */
-static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
- {
- .pa_start = 0x44E09000,
- .pa_end = 0x44E09000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_uart1_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_uart1_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart2 */
-static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
- {
- .pa_start = 0x48022000,
- .pa_end = 0x48022000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart2_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_uart2_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart3 */
-static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
- {
- .pa_start = 0x48024000,
- .pa_end = 0x48024000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart3_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_uart3_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart4 */
-static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
- {
- .pa_start = 0x481A6000,
- .pa_end = 0x481A6000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart4_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_uart4_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart5 */
-static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
- {
- .pa_start = 0x481A8000,
- .pa_end = 0x481A8000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart5_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_uart5_addr_space,
.user = OCP_USER_MPU,
};
/* l4 ls -> uart6 */
-static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
- {
- .pa_start = 0x481aa000,
- .pa_end = 0x481aa000 + SZ_8K - 1,
- .flags = ADDR_TYPE_RT,
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_uart6_hwmod,
.clk = "l4ls_gclk",
- .addr = am33xx_uart6_addr_space,
.user = OCP_USER_MPU,
};
/* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
- {
- .pa_start = 0x44e35000,
- .pa_end = 0x44e35000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
- .addr = am33xx_wd_timer1_addrs,
.user = OCP_USER_MPU,
};
/* usbss */
/* l3 s -> USBSS interface */
-static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
- {
- .name = "usbss",
- .pa_start = 0x47400000,
- .pa_end = 0x47400000 + SZ_4K - 1,
- .flags = ADDR_TYPE_RT
- },
- {
- .name = "musb0",
- .pa_start = 0x47401000,
- .pa_end = 0x47401000 + SZ_2K - 1,
- .flags = ADDR_TYPE_RT
- },
- {
- .name = "musb1",
- .pa_start = 0x47401800,
- .pa_end = 0x47401800 + SZ_2K - 1,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_usbss_hwmod,
.clk = "l3s_gclk",
- .addr = am33xx_usbss_addr_space,
.user = OCP_USER_MPU,
.flags = OCPIF_SWSUP_IDLE,
};
@@ -3518,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
&am33xx_l3_s__l4_wkup,
- &am33xx_l3_s__l4_fw,
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
@@ -3554,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_per__i2c3,
&am33xx_l4_per__mailbox,
&am33xx_l4_ls__mcasp0,
- &am33xx_l3_s__mcasp0_data,
&am33xx_l4_ls__mcasp1,
- &am33xx_l3_s__mcasp1_data,
&am33xx_l4_ls__mmc0,
&am33xx_l4_ls__mmc1,
&am33xx_l3_s__mmc2,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (10 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up Santosh Shilimkar
@ 2013-05-29 16:38 ` Santosh Shilimkar
2013-06-06 17:57 ` Paul Walmsley
2013-05-30 0:13 ` [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Tony Lindgren
[not found] ` <1369845494-30231-5-git-send-email-santosh.shilimkar@ti.com>
13 siblings, 1 reply; 38+ messages in thread
From: Santosh Shilimkar @ 2013-05-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Sricharan R <r.sricharan@ti.com>
- The IO resource information like dma request lines, irq number and
ocp address space can be populated via dt blob. So such data is stripped
from OMAP4 SOC hwmod data file.
- The devices which are still missing the device tree bindings,
address space entries are not removed yet. When such devices add
the dt bindings, respective address space data can be deleted.
- Also other unnessecary hwmods like firewalls are removed as a part of this.
The above update, results in reduction of about ~1650 lines of code.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1661 +---------------------------
1 file changed, 19 insertions(+), 1642 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 848b6dc..36dbd63 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -52,27 +52,6 @@
*/
/*
- * 'c2c_target_fw' class
- * instance(s): c2c_target_fw
- */
-static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
- .name = "c2c_target_fw",
-};
-
-/* c2c_target_fw */
-static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
- .name = "c2c_target_fw",
- .class = &omap44xx_c2c_target_fw_hwmod_class,
- .clkdm_name = "d2d_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'dmm' class
* instance(s): dmm
*/
@@ -81,16 +60,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
};
/* dmm */
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
- { .irq = 113 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_dmm_hwmod = {
.name = "dmm",
.class = &omap44xx_dmm_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
- .mpu_irqs = omap44xx_dmm_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
@@ -100,27 +73,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
};
/*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
- .name = "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod omap44xx_emif_fw_hwmod = {
- .name = "emif_fw",
- .class = &omap44xx_emif_fw_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'l3' class
* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
*/
@@ -143,17 +95,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
};
/* l3_main_1 */
-static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
- { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
- { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.name = "l3_main_1",
.class = &omap44xx_l3_hwmod_class,
.clkdm_name = "l3_1_clkdm",
- .mpu_irqs = omap44xx_l3_main_1_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
@@ -326,29 +271,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
};
/* aess */
-static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
- { .irq = 99 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
- { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
- { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_aess_hwmod = {
.name = "aess",
.class = &omap44xx_aess_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_aess_irqs,
- .sdma_reqs = omap44xx_aess_sdma_reqs,
.main_clk = "aess_fclk",
.prcm = {
.omap4 = {
@@ -371,22 +297,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
};
/* c2c */
-static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
- { .irq = 88 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
- { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_c2c_hwmod = {
.name = "c2c",
.class = &omap44xx_c2c_hwmod_class,
.clkdm_name = "d2d_clkdm",
- .mpu_irqs = omap44xx_c2c_irqs,
- .sdma_reqs = omap44xx_c2c_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
@@ -449,16 +363,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
};
/* ctrl_module_core */
-static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
- { .irq = 8 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
.name = "ctrl_module_core",
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
- .mpu_irqs = omap44xx_ctrl_module_core_irqs,
.prcm = {
.omap4 = {
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
@@ -556,7 +464,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
.lch_count = 32,
};
-/* dma_system */
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
@@ -565,6 +472,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
{ .irq = -1 }
};
+/* dma_system */
static struct omap_hwmod omap44xx_dma_system_hwmod = {
.name = "dma_system",
.class = &omap44xx_dma_hwmod_class,
@@ -601,22 +509,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
};
/* dmic */
-static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
- { .irq = 114 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
- { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic",
.class = &omap44xx_dmic_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_dmic_irqs,
- .sdma_reqs = omap44xx_dmic_sdma_reqs,
.main_clk = "func_dmic_abe_gfclk",
.prcm = {
.omap4 = {
@@ -637,11 +533,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
};
/* dsp */
-static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
- { .irq = 28 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
};
@@ -650,7 +541,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "dsp",
.class = &omap44xx_dsp_hwmod_class,
.clkdm_name = "tesla_clkdm",
- .mpu_irqs = omap44xx_dsp_irqs,
.rst_lines = omap44xx_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dpll_iva_m4x2_ck",
@@ -728,16 +618,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
};
/* dss_dispc */
-static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
- { .irq = 25 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
- { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
.manager_count = 3,
.has_framedonetv_irq = 1
@@ -747,8 +627,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap44xx_dispc_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
- .mpu_irqs = omap44xx_dss_dispc_irqs,
- .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
@@ -781,16 +659,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
};
/* dss_dsi1 */
-static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
- { .irq = 53 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
- { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
@@ -799,8 +667,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
.name = "dss_dsi1",
.class = &omap44xx_dsi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
- .mpu_irqs = omap44xx_dss_dsi1_irqs,
- .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
@@ -813,16 +679,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
};
/* dss_dsi2 */
-static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
- { .irq = 84 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
- { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
@@ -831,8 +687,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
.name = "dss_dsi2",
.class = &omap44xx_dsi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
- .mpu_irqs = omap44xx_dss_dsi2_irqs,
- .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
@@ -865,16 +719,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
};
/* dss_hdmi */
-static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
- { .irq = 101 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
- { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
{ .role = "sys_clk", .clk = "dss_sys_clk" },
};
@@ -888,8 +732,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
* set idle mode by software.
*/
.flags = HWMOD_SWSUP_SIDLE,
- .mpu_irqs = omap44xx_dss_hdmi_irqs,
- .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
.main_clk = "dss_48mhz_clk",
.prcm = {
.omap4 = {
@@ -922,11 +764,6 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
};
/* dss_rfbi */
-static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
- { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
{ .role = "ick", .clk = "dss_fck" },
};
@@ -935,7 +772,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap44xx_rfbi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
- .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
.main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
@@ -992,16 +828,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
};
/* elm */
-static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
- { .irq = 4 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_elm_hwmod = {
.name = "elm",
.class = &omap44xx_elm_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_elm_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
@@ -1025,17 +855,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
};
/* emif1 */
-static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
- { .irq = 110 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_emif1_hwmod = {
.name = "emif1",
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .mpu_irqs = omap44xx_emif1_irqs,
.main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
@@ -1047,17 +871,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
};
/* emif2 */
-static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
- { .irq = 111 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_emif2_hwmod = {
.name = "emif2",
.class = &omap44xx_emif_hwmod_class,
.clkdm_name = "l3_emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .mpu_irqs = omap44xx_emif2_irqs,
.main_clk = "ddrphy_ck",
.prcm = {
.omap4 = {
@@ -1098,16 +916,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
};
/* fdif */
-static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
- { .irq = 69 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_fdif_hwmod = {
.name = "fdif",
.class = &omap44xx_fdif_hwmod_class,
.clkdm_name = "iss_clkdm",
- .mpu_irqs = omap44xx_fdif_irqs,
.main_clk = "fdif_fck",
.prcm = {
.omap4 = {
@@ -1148,11 +960,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
- { .irq = 29 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
@@ -1161,7 +968,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = omap44xx_gpio1_irqs,
.main_clk = "l4_wkup_clk_mux_ck",
.prcm = {
.omap4 = {
@@ -1176,11 +982,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
};
/* gpio2 */
-static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
- { .irq = 30 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
@@ -1190,7 +991,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap44xx_gpio2_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
@@ -1205,11 +1005,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
};
/* gpio3 */
-static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
- { .irq = 31 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
@@ -1219,7 +1014,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap44xx_gpio3_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
@@ -1234,11 +1028,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
};
/* gpio4 */
-static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
- { .irq = 32 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbclk" },
};
@@ -1248,7 +1037,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap44xx_gpio4_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
@@ -1263,11 +1051,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
};
/* gpio5 */
-static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
- { .irq = 33 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio5_dbclk" },
};
@@ -1277,7 +1060,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap44xx_gpio5_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
@@ -1292,11 +1074,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
};
/* gpio6 */
-static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
- { .irq = 34 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio6_dbclk" },
};
@@ -1306,7 +1083,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.class = &omap44xx_gpio_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap44xx_gpio6_irqs,
.main_clk = "l4_div_ck",
.prcm = {
.omap4 = {
@@ -1341,16 +1117,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
};
/* gpmc */
-static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
- { .irq = 20 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
- { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_gpmc_hwmod = {
.name = "gpmc",
.class = &omap44xx_gpmc_hwmod_class,
@@ -1364,8 +1130,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
* HWMOD_INIT_NO_RESET should be removed ASAP.
*/
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .mpu_irqs = omap44xx_gpmc_irqs,
- .sdma_reqs = omap44xx_gpmc_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
@@ -1396,16 +1160,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
};
/* gpu */
-static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
- { .irq = 21 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_gpu_hwmod = {
.name = "gpu",
.class = &omap44xx_gpu_hwmod_class,
.clkdm_name = "l3_gfx_clkdm",
- .mpu_irqs = omap44xx_gpu_irqs,
.main_clk = "sgx_clk_mux",
.prcm = {
.omap4 = {
@@ -1436,17 +1194,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
};
/* hdq1w */
-static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
- { .irq = 58 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_hdq1w_hwmod = {
.name = "hdq1w",
.class = &omap44xx_hdq1w_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
- .mpu_irqs = omap44xx_hdq1w_irqs,
.main_clk = "func_12m_fclk",
.prcm = {
.omap4 = {
@@ -1482,18 +1234,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
};
/* hsi */
-static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
- { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
- { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
- { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_hsi_hwmod = {
.name = "hsi",
.class = &omap44xx_hsi_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap44xx_hsi_irqs,
.main_clk = "hsi_fck",
.prcm = {
.omap4 = {
@@ -1533,24 +1277,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
};
/* i2c1 */
-static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
- { .irq = 56 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_i2c1_hwmod = {
.name = "i2c1",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_i2c1_irqs,
- .sdma_reqs = omap44xx_i2c1_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
@@ -1563,24 +1294,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
};
/* i2c2 */
-static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
- { .irq = 57 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_i2c2_hwmod = {
.name = "i2c2",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_i2c2_irqs,
- .sdma_reqs = omap44xx_i2c2_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
@@ -1593,24 +1311,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
};
/* i2c3 */
-static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
- { .irq = 61 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
- { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_i2c3_hwmod = {
.name = "i2c3",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_i2c3_irqs,
- .sdma_reqs = omap44xx_i2c3_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
@@ -1623,24 +1328,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
};
/* i2c4 */
-static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
- { .irq = 62 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
- { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_i2c4_hwmod = {
.name = "i2c4",
.class = &omap44xx_i2c_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_i2c4_irqs,
- .sdma_reqs = omap44xx_i2c4_sdma_reqs,
.main_clk = "func_96m_fclk",
.prcm = {
.omap4 = {
@@ -1662,11 +1354,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
};
/* ipu */
-static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
- { .irq = 100 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "cpu0", .rst_shift = 0 },
{ .name = "cpu1", .rst_shift = 1 },
@@ -1676,7 +1363,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu",
.class = &omap44xx_ipu_hwmod_class,
.clkdm_name = "ducati_clkdm",
- .mpu_irqs = omap44xx_ipu_irqs,
.rst_lines = omap44xx_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ducati_clk_mux_ck",
@@ -1721,19 +1407,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
};
/* iss */
-static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
- { .irq = 24 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
- { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
- { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
- { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
- { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
};
@@ -1742,8 +1415,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
.name = "iss",
.class = &omap44xx_iss_hwmod_class,
.clkdm_name = "iss_clkdm",
- .mpu_irqs = omap44xx_iss_irqs,
- .sdma_reqs = omap44xx_iss_sdma_reqs,
.main_clk = "ducati_clk_mux_ck",
.prcm = {
.omap4 = {
@@ -1766,13 +1437,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
};
/* iva */
-static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
- { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
- { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
- { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
{ .name = "seq0", .rst_shift = 0 },
{ .name = "seq1", .rst_shift = 1 },
@@ -1783,7 +1447,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
.name = "iva",
.class = &omap44xx_iva_hwmod_class,
.clkdm_name = "ivahd_clkdm",
- .mpu_irqs = omap44xx_iva_irqs,
.rst_lines = omap44xx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
.main_clk = "dpll_iva_m5x2_ck",
@@ -1820,16 +1483,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
};
/* kbd */
-static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
- { .irq = 120 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd",
.class = &omap44xx_kbd_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = omap44xx_kbd_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
@@ -1861,16 +1518,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
};
/* mailbox */
-static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
- { .irq = 26 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
- .mpu_irqs = omap44xx_mailbox_irqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
@@ -1903,24 +1554,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
};
/* mcasp */
-static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
- { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
- { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
- { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
- { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mcasp_hwmod = {
.name = "mcasp",
.class = &omap44xx_mcasp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_mcasp_irqs,
- .sdma_reqs = omap44xx_mcasp_sdma_reqs,
.main_clk = "func_mcasp_abe_gfclk",
.prcm = {
.omap4 = {
@@ -1951,17 +1588,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
};
/* mcbsp1 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
- { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
@@ -1971,8 +1597,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_mcbsp1_irqs,
- .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
.main_clk = "func_mcbsp1_gfclk",
.prcm = {
.omap4 = {
@@ -1986,17 +1610,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
};
/* mcbsp2 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
- { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
@@ -2006,8 +1619,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_mcbsp2_irqs,
- .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
.main_clk = "func_mcbsp2_gfclk",
.prcm = {
.omap4 = {
@@ -2021,17 +1632,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
};
/* mcbsp3 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
- { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
- { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
@@ -2041,8 +1641,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_mcbsp3_irqs,
- .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
.main_clk = "func_mcbsp3_gfclk",
.prcm = {
.omap4 = {
@@ -2056,17 +1654,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
};
/* mcbsp4 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
- { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
- { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
@@ -2076,8 +1663,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mcbsp4_irqs,
- .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
.main_clk = "per_mcbsp4_gfclk",
.prcm = {
.omap4 = {
@@ -2112,17 +1697,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
};
/* mcpdm */
-static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
- { .irq = 112 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
- { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
- { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mcpdm_hwmod = {
.name = "mcpdm",
.class = &omap44xx_mcpdm_hwmod_class,
@@ -2139,8 +1713,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
* results 'slow motion' audio playback.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .mpu_irqs = omap44xx_mcpdm_irqs,
- .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
.main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {
@@ -2174,23 +1746,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
};
/* mcspi1 */
-static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
- { .irq = 65 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
- { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
- { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
- { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
- { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
- { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
- { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
/* mcspi1 dev_attr */
static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
.num_chipselect = 4,
@@ -2200,8 +1755,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mcspi1_irqs,
- .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2214,19 +1767,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
};
/* mcspi2 */
-static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
- { .irq = 66 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
- { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
- { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
/* mcspi2 dev_attr */
static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
.num_chipselect = 2,
@@ -2236,8 +1776,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mcspi2_irqs,
- .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2250,19 +1788,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
};
/* mcspi3 */
-static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
- { .irq = 91 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
- { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
- { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
/* mcspi3 dev_attr */
static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
.num_chipselect = 2,
@@ -2272,8 +1797,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mcspi3_irqs,
- .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2286,17 +1809,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
};
/* mcspi4 */
-static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
- { .irq = 48 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
/* mcspi4 dev_attr */
static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
.num_chipselect = 1,
@@ -2306,8 +1818,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap44xx_mcspi_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mcspi4_irqs,
- .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2342,17 +1852,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
};
/* mmc1 */
-static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
- { .irq = 83 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
/* mmc1 dev_attr */
static struct omap_mmc_dev_attr mmc1_dev_attr = {
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -2362,8 +1861,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
.name = "mmc1",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap44xx_mmc1_irqs,
- .sdma_reqs = omap44xx_mmc1_sdma_reqs,
.main_clk = "hsmmc1_fclk",
.prcm = {
.omap4 = {
@@ -2376,23 +1873,10 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
};
/* mmc2 */
-static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
- { .irq = 86 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap44xx_mmc2_irqs,
- .sdma_reqs = omap44xx_mmc2_sdma_reqs,
.main_clk = "hsmmc2_fclk",
.prcm = {
.omap4 = {
@@ -2404,23 +1888,10 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
};
/* mmc3 */
-static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
- { .irq = 94 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
- { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mmc3_irqs,
- .sdma_reqs = omap44xx_mmc3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2432,23 +1903,10 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
};
/* mmc4 */
-static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
- { .irq = 96 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
- { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mmc4_irqs,
- .sdma_reqs = omap44xx_mmc4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2460,23 +1918,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
};
/* mmc5 */
-static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
- { .irq = 59 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
- { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap44xx_mmc_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_mmc5_irqs,
- .sdma_reqs = omap44xx_mmc5_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -2517,11 +1962,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
};
static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
- { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
{ .name = "mmu_cache", .rst_shift = 2 },
};
@@ -2548,7 +1988,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
.name = "mmu_ipu",
.class = &omap44xx_mmu_hwmod_class,
.clkdm_name = "ducati_clkdm",
- .mpu_irqs = omap44xx_mmu_ipu_irqs,
.rst_lines = omap44xx_mmu_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
.main_clk = "ducati_clk_mux_ck",
@@ -2572,11 +2011,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
};
static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
- { .irq = 28 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
{ .name = "mmu_cache", .rst_shift = 1 },
};
@@ -2603,7 +2037,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
.name = "mmu_dsp",
.class = &omap44xx_mmu_hwmod_class,
.clkdm_name = "tesla_clkdm",
- .mpu_irqs = omap44xx_mmu_dsp_irqs,
.rst_lines = omap44xx_mmu_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
.main_clk = "dpll_iva_m4x2_ck",
@@ -2628,21 +2061,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
};
/* mpu */
-static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
- { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
- { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
- { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
- { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
- { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_mpu_hwmod = {
.name = "mpu",
.class = &omap44xx_mpu_hwmod_class,
.clkdm_name = "mpuss_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .mpu_irqs = omap44xx_mpu_irqs,
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
@@ -2696,20 +2119,9 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
};
/* ocp2scp dev_attr */
-static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
- {
- .name = "usb_phy",
- .start = 0x4a0ad080,
- .end = 0x4a0ae000,
- .flags = IORESOURCE_MEM,
- },
- { }
-};
-
static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
{
.drv_name = "omap-usb2",
- .res = omap44xx_usb_phy_and_pll_addrs,
},
{ }
};
@@ -2788,11 +2200,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
};
/* prm */
-static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
- { .irq = 11 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
{ .name = "rst_global_warm_sw", .rst_shift = 0 },
{ .name = "rst_global_cold_sw", .rst_shift = 1 },
@@ -2801,7 +2208,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
static struct omap_hwmod omap44xx_prm_hwmod = {
.name = "prm",
.class = &omap44xx_prcm_hwmod_class,
- .mpu_irqs = omap44xx_prm_irqs,
.rst_lines = omap44xx_prm_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
};
@@ -2872,23 +2278,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
};
/* slimbus1 */
-static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
- { .irq = 97 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
- { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
- { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
- { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
- { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
- { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
- { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
@@ -2900,8 +2289,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
.name = "slimbus1",
.class = &omap44xx_slimbus_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_slimbus1_irqs,
- .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
@@ -2914,23 +2301,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
};
/* slimbus2 */
-static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
- { .irq = 98 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
- { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
- { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
- { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
- { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
- { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
- { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
- { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
@@ -2941,8 +2311,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
.name = "slimbus2",
.class = &omap44xx_slimbus_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_slimbus2_irqs,
- .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
@@ -2985,16 +2353,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
.sensor_voltdm_name = "core",
};
-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
- { .irq = 19 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
- .mpu_irqs = omap44xx_smartreflex_core_irqs,
.main_clk = "smartreflex_core_fck",
.prcm = {
@@ -3012,16 +2374,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
.sensor_voltdm_name = "iva",
};
-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
- { .irq = 102 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
- .mpu_irqs = omap44xx_smartreflex_iva_irqs,
.main_clk = "smartreflex_iva_fck",
.prcm = {
.omap4 = {
@@ -3038,16 +2394,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
.sensor_voltdm_name = "mpu",
};
-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
- { .irq = 18 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class,
.clkdm_name = "l4_ao_clkdm",
- .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
.main_clk = "smartreflex_mpu_fck",
.prcm = {
.omap4 = {
@@ -3155,17 +2505,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
};
/* timer1 */
-static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
- { .irq = 37 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_timer1_irqs,
.main_clk = "dmt1_clk_mux",
.prcm = {
.omap4 = {
@@ -3178,17 +2522,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
};
/* timer2 */
-static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
- { .irq = 38 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_timer2_irqs,
.main_clk = "cm2_dm2_mux",
.prcm = {
.omap4 = {
@@ -3200,16 +2538,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
};
/* timer3 */
-static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
- { .irq = 39 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_timer3_irqs,
.main_clk = "cm2_dm3_mux",
.prcm = {
.omap4 = {
@@ -3221,16 +2553,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
};
/* timer4 */
-static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
- { .irq = 40 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer4_hwmod = {
.name = "timer4",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_timer4_irqs,
.main_clk = "cm2_dm4_mux",
.prcm = {
.omap4 = {
@@ -3242,16 +2568,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
};
/* timer5 */
-static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
- { .irq = 41 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_timer5_irqs,
.main_clk = "timer5_sync_mux",
.prcm = {
.omap4 = {
@@ -3264,16 +2584,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
};
/* timer6 */
-static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
- { .irq = 42 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_timer6_irqs,
.main_clk = "timer6_sync_mux",
.prcm = {
.omap4 = {
@@ -3286,16 +2600,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
};
/* timer7 */
-static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
- { .irq = 43 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_timer7_irqs,
.main_clk = "timer7_sync_mux",
.prcm = {
.omap4 = {
@@ -3308,16 +2616,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
};
/* timer8 */
-static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
- { .irq = 44 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_timer8_irqs,
.main_clk = "timer8_sync_mux",
.prcm = {
.omap4 = {
@@ -3330,16 +2632,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
};
/* timer9 */
-static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
- { .irq = 45 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_timer9_irqs,
.main_clk = "cm2_dm9_mux",
.prcm = {
.omap4 = {
@@ -3352,17 +2648,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
};
/* timer10 */
-static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
- { .irq = 46 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .mpu_irqs = omap44xx_timer10_irqs,
.main_clk = "cm2_dm10_mux",
.prcm = {
.omap4 = {
@@ -3375,16 +2665,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
};
/* timer11 */
-static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
- { .irq = 47 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11",
.class = &omap44xx_timer_hwmod_class,
.clkdm_name = "l4_per_clkdm",
- .mpu_irqs = omap44xx_timer11_irqs,
.main_clk = "cm2_dm11_mux",
.prcm = {
.omap4 = {
@@ -3419,24 +2703,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
};
/* uart1 */
-static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
- { .irq = 72 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
- { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_uart1_hwmod = {
.name = "uart1",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = omap44xx_uart1_irqs,
- .sdma_reqs = omap44xx_uart1_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -3448,24 +2719,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
};
/* uart2 */
-static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
- { .irq = 73 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
- { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_uart2_hwmod = {
.name = "uart2",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = omap44xx_uart2_irqs,
- .sdma_reqs = omap44xx_uart2_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -3477,25 +2735,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
};
/* uart3 */
-static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
- { .irq = 74 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
- { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_uart3_hwmod = {
.name = "uart3",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = omap44xx_uart3_irqs,
- .sdma_reqs = omap44xx_uart3_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -3507,24 +2752,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
};
/* uart4 */
-static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
- { .irq = 70 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
- { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
- { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod omap44xx_uart4_hwmod = {
.name = "uart4",
.class = &omap44xx_uart_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SWSUP_SIDLE_ACT,
- .mpu_irqs = omap44xx_uart4_irqs,
- .sdma_reqs = omap44xx_uart4_sdma_reqs,
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
@@ -3563,17 +2795,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
};
/* usb_host_fs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
- { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
- { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
.name = "usb_host_fs",
.class = &omap44xx_usb_host_fs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap44xx_usb_host_fs_irqs,
.main_clk = "usb_host_fs_fck",
.prcm = {
.omap4 = {
@@ -3607,12 +2832,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
};
/* usb_host_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
- { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
- { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.name = "usb_host_hs",
.class = &omap44xx_usb_host_hs_hwmod_class,
@@ -3625,7 +2844,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .mpu_irqs = omap44xx_usb_host_hs_irqs,
/*
* Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3700,12 +2918,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
};
/* usb_otg_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
- { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
- { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};
@@ -3715,7 +2927,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.class = &omap44xx_usb_otg_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .mpu_irqs = omap44xx_usb_otg_hs_irqs,
.main_clk = "usb_otg_hs_ick",
.prcm = {
.omap4 = {
@@ -3749,16 +2960,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
.sysc = &omap44xx_usb_tll_hs_sysc,
};
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
- { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
.name = "usb_tll_hs",
.class = &omap44xx_usb_tll_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
- .mpu_irqs = omap44xx_usb_tll_hs_irqs,
.main_clk = "usb_tll_hs_ick",
.prcm = {
.omap4 = {
@@ -3794,16 +2999,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
};
/* wd_timer2 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
- { .irq = 80 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
- .mpu_irqs = omap44xx_wd_timer2_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
@@ -3815,16 +3014,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
};
/* wd_timer3 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
- { .irq = 36 + OMAP44XX_IRQ_GIC_START },
- { .irq = -1 }
-};
-
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
- .mpu_irqs = omap44xx_wd_timer3_irqs,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
@@ -3840,32 +3033,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
* interfaces
*/
-static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
- {
- .pa_start = 0x4a204000,
- .pa_end = 0x4a2040ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* c2c -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
- .master = &omap44xx_c2c_hwmod,
- .slave = &omap44xx_c2c_target_fw_hwmod,
- .clk = "div_core_ck",
- .addr = omap44xx_c2c_target_fw_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* l4_cfg -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_c2c_target_fw_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -3874,55 +3041,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
- {
- .pa_start = 0x4e000000,
- .pa_end = 0x4e0007ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* mpu -> dmm */
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_dmm_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_dmm_addrs,
- .user = OCP_USER_MPU,
-};
-
-/* c2c -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
- .master = &omap44xx_c2c_hwmod,
- .slave = &omap44xx_emif_fw_hwmod,
- .clk = "div_core_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
- .master = &omap44xx_dmm_hwmod,
- .slave = &omap44xx_emif_fw_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
- {
- .pa_start = 0x4a20c000,
- .pa_end = 0x4a20c0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_emif_fw_hwmod,
- .clk = "l4_div_ck",
- .addr = omap44xx_emif_fw_addrs,
.user = OCP_USER_MPU,
};
@@ -3998,32 +3121,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
- {
- .pa_start = 0x44000000,
- .pa_end = 0x44000fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
.master = &omap44xx_mpu_hwmod,
.slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_l3_main_1_addrs,
.user = OCP_USER_MPU,
};
-/* c2c_target_fw -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
- .master = &omap44xx_c2c_target_fw_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* debugss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
.master = &omap44xx_debugss_hwmod,
@@ -4088,21 +3193,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
- {
- .pa_start = 0x44800000,
- .pa_end = 0x44801fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.master = &omap44xx_l3_main_1_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_l3_main_2_addrs,
.user = OCP_USER_MPU,
};
@@ -4138,21 +3233,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
- {
- .pa_start = 0x45000000,
- .pa_end = 0x45000fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.master = &omap44xx_l3_main_1_hwmod,
.slave = &omap44xx_l3_main_3_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_l3_main_3_addrs,
.user = OCP_USER_MPU,
};
@@ -4236,21 +3321,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
- {
- .pa_start = 0x4a102000,
- .pa_end = 0x4a10207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_cfg -> ocp_wp_noc */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_ocp_wp_noc_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_ocp_wp_noc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4340,21 +3415,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
- {
- .pa_start = 0x4a304000,
- .pa_end = 0x4a30401f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_counter_32k_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_counter_32k_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4430,21 +3495,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
- {
- .pa_start = 0x54160000,
- .pa_end = 0x54167fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l3_instr -> debugss */
static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
.master = &omap44xx_l3_instr_hwmod,
.slave = &omap44xx_debugss_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_debugss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4466,41 +3521,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x4012e000,
- .pa_end = 0x4012e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> dmic */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_dmic_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x4902e000,
- .pa_end = 0x4902e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> dmic (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_dmic_dma_addrs,
.user = OCP_USER_SDMA,
};
@@ -4798,42 +3831,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
- {
- .pa_start = 0x4c000000,
- .pa_end = 0x4c0000ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* emif_fw -> emif1 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
- .master = &omap44xx_emif_fw_hwmod,
- .slave = &omap44xx_emif1_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_emif1_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
- {
- .pa_start = 0x4d000000,
- .pa_end = 0x4d0000ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
-/* emif_fw -> emif2 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
- .master = &omap44xx_emif_fw_hwmod,
- .slave = &omap44xx_emif2_hwmod,
- .clk = "l3_div_ck",
- .addr = omap44xx_emif2_addrs,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
{
.pa_start = 0x4a10a000,
@@ -4852,129 +3849,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
- {
- .pa_start = 0x4a310000,
- .pa_end = 0x4a3101ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_gpio1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_gpio1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
- {
- .pa_start = 0x48055000,
- .pa_end = 0x480551ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_gpio2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
- {
- .pa_start = 0x48057000,
- .pa_end = 0x480571ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_gpio3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
- {
- .pa_start = 0x48059000,
- .pa_end = 0x480591ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_gpio4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
- {
- .pa_start = 0x4805b000,
- .pa_end = 0x4805b1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio5_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_gpio5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
- {
- .pa_start = 0x4805d000,
- .pa_end = 0x4805d1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_gpio6_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_gpio6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
- {
- .pa_start = 0x50000000,
- .pa_end = 0x500003ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_gpmc_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_gpmc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -5032,75 +3959,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
- {
- .pa_start = 0x48070000,
- .pa_end = 0x480700ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c1_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_i2c1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
- {
- .pa_start = 0x48072000,
- .pa_end = 0x480720ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_i2c2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
- {
- .pa_start = 0x48060000,
- .pa_end = 0x480600ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> i2c3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_i2c3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
- {
- .pa_start = 0x48350000,
- .pa_end = 0x483500ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> i2c4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_i2c4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_i2c4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -5138,39 +4025,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
.user = OCP_USER_IVA,
};
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
- {
- .pa_start = 0x5a000000,
- .pa_end = 0x5a07ffff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l3_main_2 -> iva */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_iva_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_iva_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
- {
- .pa_start = 0x4a31c000,
- .pa_end = 0x4a31c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> kbd */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_kbd_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_kbd_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -5228,335 +4095,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40122000,
- .pa_end = 0x401220ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp1_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49022000,
- .pa_end = 0x490220ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp1 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp1_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40124000,
- .pa_end = 0x401240ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp2_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49024000,
- .pa_end = 0x490240ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp2 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp2_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40126000,
- .pa_end = 0x401260ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp3_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49026000,
- .pa_end = 0x490260ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcbsp3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcbsp3_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
- {
- .pa_start = 0x48096000,
- .pa_end = 0x480960ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcbsp4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mcbsp4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x40132000,
- .pa_end = 0x4013207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcpdm_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
- {
- .name = "dma",
- .pa_start = 0x49032000,
- .pa_end = 0x4903207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> mcpdm (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_mcpdm_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
- {
- .pa_start = 0x48098000,
- .pa_end = 0x480981ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi1_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mcspi1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
- {
- .pa_start = 0x4809a000,
- .pa_end = 0x4809a1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mcspi2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
- {
- .pa_start = 0x480b8000,
- .pa_end = 0x480b81ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mcspi3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
- {
- .pa_start = 0x480ba000,
- .pa_end = 0x480ba1ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcspi4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mcspi4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
- {
- .pa_start = 0x4809c000,
- .pa_end = 0x4809c3ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mmc1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc1_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mmc1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
- {
- .pa_start = 0x480b4000,
- .pa_end = 0x480b43ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mmc2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mmc2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
- {
- .pa_start = 0x480ad000,
- .pa_end = 0x480ad3ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mmc3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mmc3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
- {
- .pa_start = 0x480d1000,
- .pa_end = 0x480d13ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mmc4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mmc4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
- {
- .pa_start = 0x480d5000,
- .pa_end = 0x480d53ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> mmc5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mmc5_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_mmc5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -5568,111 +4247,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
- {
- .pa_start = 0x4a0ad000,
- .pa_end = 0x4a0ad01f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_cfg -> ocp2scp_usb_phy */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_ocp2scp_usb_phy_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_ocp2scp_usb_phy_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
- {
- .pa_start = 0x48243000,
- .pa_end = 0x48243fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* mpu_private -> prcm_mpu */
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
.master = &omap44xx_mpu_private_hwmod,
.slave = &omap44xx_prcm_mpu_hwmod,
.clk = "l3_div_ck",
- .addr = omap44xx_prcm_mpu_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
- {
- .pa_start = 0x4a004000,
- .pa_end = 0x4a004fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> cm_core_aon */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_cm_core_aon_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_cm_core_aon_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
- {
- .pa_start = 0x4a008000,
- .pa_end = 0x4a009fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_cfg -> cm_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_cm_core_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_cm_core_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
- {
- .pa_start = 0x4a306000,
- .pa_end = 0x4a307fff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> prm */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_prm_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_prm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
- {
- .pa_start = 0x4a30a000,
- .pa_end = 0x4a30a7ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> scrm */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_scrm_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_scrm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -5810,447 +4429,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
- {
- .pa_start = 0x4a318000,
- .pa_end = 0x4a31807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_timer1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_timer1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
- {
- .pa_start = 0x48032000,
- .pa_end = 0x4803207f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
- {
- .pa_start = 0x48034000,
- .pa_end = 0x4803407f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
- {
- .pa_start = 0x48036000,
- .pa_end = 0x4803607f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
- {
- .pa_start = 0x40138000,
- .pa_end = 0x4013807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer5 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer5_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
- {
- .pa_start = 0x49038000,
- .pa_end = 0x4903807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer5 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer5_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
- {
- .pa_start = 0x4013a000,
- .pa_end = 0x4013a07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer6 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer6_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
- {
- .pa_start = 0x4903a000,
- .pa_end = 0x4903a07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer6 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer6_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
- {
- .pa_start = 0x4013c000,
- .pa_end = 0x4013c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer7 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer7_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
- {
- .pa_start = 0x4903c000,
- .pa_end = 0x4903c07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer7 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer7_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
- {
- .pa_start = 0x4013e000,
- .pa_end = 0x4013e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer8 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer8_addrs,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
- {
- .pa_start = 0x4903e000,
- .pa_end = 0x4903e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_abe -> timer8 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
- .addr = omap44xx_timer8_dma_addrs,
.user = OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
- {
- .pa_start = 0x4803e000,
- .pa_end = 0x4803e07f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer9 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer9_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer9_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
- {
- .pa_start = 0x48086000,
- .pa_end = 0x4808607f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer10 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer10_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
- {
- .pa_start = 0x48088000,
- .pa_end = 0x4808807f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> timer11 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_timer11_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
- {
- .pa_start = 0x4806a000,
- .pa_end = 0x4806a0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> uart1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart1_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_uart1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
- {
- .pa_start = 0x4806c000,
- .pa_end = 0x4806c0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> uart2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart2_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_uart2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
- {
- .pa_start = 0x48020000,
- .pa_end = 0x480200ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> uart3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart3_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_uart3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
- {
- .pa_start = 0x4806e000,
- .pa_end = 0x4806e0ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_per -> uart4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_uart4_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_uart4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
- {
- .pa_start = 0x4a0a9000,
- .pa_end = 0x4a0a93ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_cfg -> usb_host_fs */
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_host_fs_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_host_fs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
- {
- .name = "uhh",
- .pa_start = 0x4a064000,
- .pa_end = 0x4a0647ff,
- .flags = ADDR_TYPE_RT
- },
- {
- .name = "ohci",
- .pa_start = 0x4a064800,
- .pa_end = 0x4a064bff,
- },
- {
- .name = "ehci",
- .pa_start = 0x4a064c00,
- .pa_end = 0x4a064fff,
- },
- {}
-};
-
/* l4_cfg -> usb_host_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_host_hs_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_host_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
- {
- .pa_start = 0x4a0ab000,
- .pa_end = 0x4a0ab7ff,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_cfg -> usb_otg_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_otg_hs_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_otg_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
- {
- .name = "tll",
- .pa_start = 0x4a062000,
- .pa_end = 0x4a063fff,
- .flags = ADDR_TYPE_RT
- },
- {}
-};
-
/* l4_cfg -> usb_tll_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_tll_hs_hwmod,
.clk = "l4_div_ck",
- .addr = omap44xx_usb_tll_hs_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
- {
- .pa_start = 0x4a314000,
- .pa_end = 0x4a31407f,
- .flags = ADDR_TYPE_RT
- },
- { }
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck",
- .addr = omap44xx_wd_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -6290,14 +4657,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.user = OCP_USER_SDMA,
};
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_emif1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_emif2_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
- &omap44xx_c2c__c2c_target_fw,
- &omap44xx_l4_cfg__c2c_target_fw,
&omap44xx_l3_main_1__dmm,
&omap44xx_mpu__dmm,
- &omap44xx_c2c__emif_fw,
- &omap44xx_dmm__emif_fw,
- &omap44xx_l4_cfg__emif_fw,
&omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr,
@@ -6308,7 +4686,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_mmc1__l3_main_1,
&omap44xx_mmc2__l3_main_1,
&omap44xx_mpu__l3_main_1,
- &omap44xx_c2c_target_fw__l3_main_2,
&omap44xx_debugss__l3_main_2,
&omap44xx_dma_system__l3_main_2,
&omap44xx_fdif__l3_main_2,
@@ -6364,8 +4741,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_2__dss_venc,
&omap44xx_l4_per__dss_venc,
&omap44xx_l4_per__elm,
- &omap44xx_emif_fw__emif1,
- &omap44xx_emif_fw__emif2,
&omap44xx_l4_cfg__fdif,
&omap44xx_l4_wkup__gpio1,
&omap44xx_l4_per__gpio2,
@@ -6450,6 +4825,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_wkup__wd_timer2,
&omap44xx_l4_abe__wd_timer3,
&omap44xx_l4_abe__wd_timer3_dma,
+ &omap44xx_mpu__emif1,
+ &omap44xx_mpu__emif2,
NULL,
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
` (11 preceding siblings ...)
2013-05-29 16:38 ` [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file Santosh Shilimkar
@ 2013-05-30 0:13 ` Tony Lindgren
2013-05-30 0:24 ` Tony Lindgren
[not found] ` <1369845494-30231-5-git-send-email-santosh.shilimkar@ti.com>
13 siblings, 1 reply; 38+ messages in thread
From: Tony Lindgren @ 2013-05-30 0:13 UTC (permalink / raw)
To: linux-arm-kernel
* Santosh Shilimkar <santosh.shilimkar@ti.com> [130529 09:44]:
> Tony, Paul,
>
> Here is another attempt to send the SOC data files for OMAP5 based devices.
> As aligned on list, I have dropped clock data from the series.
> That means for the boot, one clock data patch needs to be applied.
> It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.
>
> With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
> up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
> is also targeted as DT only, its hwmod data files is also cleaned up.
> Diffstat looks something like below.
>
> 27 files changed, 9013 insertions(+), 2764 deletions(-)
>
> One can easily notice that the OMAP5 SOC data has significantly come down
> becasue of iospace and rest of the hwmod clean-up.
Yes that's great. I'd like to take the last three patches into my yet to
be posted omap-for-v3.11/cleanup branch with the omap4 legacy boot files
now that -rc3 is out and the GPIO fix dependency has cleared.
Paul, care to ack those three? Then you probably want to review queue
the rest I presume.
Regards,
Tony
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11
2013-05-30 0:13 ` [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Tony Lindgren
@ 2013-05-30 0:24 ` Tony Lindgren
0 siblings, 0 replies; 38+ messages in thread
From: Tony Lindgren @ 2013-05-30 0:24 UTC (permalink / raw)
To: linux-arm-kernel
* Tony Lindgren <tony@atomide.com> [130529 17:19]:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [130529 09:44]:
> > Tony, Paul,
> >
> > Here is another attempt to send the SOC data files for OMAP5 based devices.
> > As aligned on list, I have dropped clock data from the series.
> > That means for the boot, one clock data patch needs to be applied.
> > It is available on my git tree in 'out_of_tree/omap5_clk_data' branch.
> >
> > With OMAP5 and AM33XX support is DT only, respective hwmod files are cleaned
> > up to remove iospace information and un-used hwmod. For 3.11 since OMAP4
> > is also targeted as DT only, its hwmod data files is also cleaned up.
> > Diffstat looks something like below.
> >
> > 27 files changed, 9013 insertions(+), 2764 deletions(-)
> >
> > One can easily notice that the OMAP5 SOC data has significantly come down
> > becasue of iospace and rest of the hwmod clean-up.
>
> Yes that's great. I'd like to take the last three patches into my yet to
> be posted omap-for-v3.11/cleanup branch with the omap4 legacy boot files
> now that -rc3 is out and the GPIO fix dependency has cleared.
>
> Paul, care to ack those three? Then you probably want to review queue
> the rest I presume.
Correction: The last two patches I mean.
Regards,
Tony
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-05-29 16:38 ` [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up Santosh Shilimkar
@ 2013-06-06 4:00 ` Paul Walmsley
2013-06-06 22:27 ` Kevin Hilman
2013-06-07 16:13 ` Tony Lindgren
0 siblings, 2 replies; 38+ messages in thread
From: Paul Walmsley @ 2013-06-06 4:00 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 29 May 2013, Santosh Shilimkar wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> AM33XX only supports DT boot mode and with addition of
> extracting module resources like, irq, dma and address space
> from DT block, so now we can remove duplicate information from
> hwmod data file.
OK, guess I'll take your word for it that it all works. The
BeagleBone-white with appended DTB hasn't booted here since v3.7.
And the BeagleBone-black with discrete DTB doesn't boot at all with
current mainline, only with the TI vendor kernel & DTB...
Acked-by: Paul Walmsley <paul@pwsan.com>
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-05-29 16:38 ` [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file Santosh Shilimkar
@ 2013-06-06 17:57 ` Paul Walmsley
2013-06-06 18:30 ` Santosh Shilimkar
0 siblings, 1 reply; 38+ messages in thread
From: Paul Walmsley @ 2013-06-06 17:57 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 29 May 2013, Santosh Shilimkar wrote:
> From: Sricharan R <r.sricharan@ti.com>
>
> - The IO resource information like dma request lines, irq number and
> ocp address space can be populated via dt blob. So such data is stripped
> from OMAP4 SOC hwmod data file.
>
> - The devices which are still missing the device tree bindings,
> address space entries are not removed yet. When such devices add
> the dt bindings, respective address space data can be deleted.
>
> - Also other unnessecary hwmods like firewalls are removed as a part of this.
>
> The above update, results in reduction of about ~1650 lines of code.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Sricharan R <r.sricharan@ti.com>
I assume that you're not autogenerating this data any more, based on
your change list above. If that's correct, please also remove
the paragraph at the top of the file:
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap at vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-06 17:57 ` Paul Walmsley
@ 2013-06-06 18:30 ` Santosh Shilimkar
2013-06-07 5:55 ` Sricharan R
0 siblings, 1 reply; 38+ messages in thread
From: Santosh Shilimkar @ 2013-06-06 18:30 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 06 June 2013 01:57 PM, Paul Walmsley wrote:
> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>
>> From: Sricharan R <r.sricharan@ti.com>
>>
>> - The IO resource information like dma request lines, irq number and
>> ocp address space can be populated via dt blob. So such data is stripped
>> from OMAP4 SOC hwmod data file.
>>
>> - The devices which are still missing the device tree bindings,
>> address space entries are not removed yet. When such devices add
>> the dt bindings, respective address space data can be deleted.
>>
>> - Also other unnessecary hwmods like firewalls are removed as a part of this.
>>
>> The above update, results in reduction of about ~1650 lines of code.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>
> I assume that you're not autogenerating this data any more, based on
> your change list above. If that's correct, please also remove
> the paragraph at the top of the file:
>
The data is auto-generated. I let Sricharan comment if it is otherwise
in the final version of the patch.
Sricharan ?
Regards,
Santosh
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-06 4:00 ` Paul Walmsley
@ 2013-06-06 22:27 ` Kevin Hilman
2013-06-07 17:01 ` Santosh Shilimkar
` (2 more replies)
2013-06-07 16:13 ` Tony Lindgren
1 sibling, 3 replies; 38+ messages in thread
From: Kevin Hilman @ 2013-06-06 22:27 UTC (permalink / raw)
To: linux-arm-kernel
Paul Walmsley <paul@pwsan.com> writes:
> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>
>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>
>> AM33XX only supports DT boot mode and with addition of
>> extracting module resources like, irq, dma and address space
>> from DT block, so now we can remove duplicate information from
>> hwmod data file.
>
> OK, guess I'll take your word for it that it all works. The
> BeagleBone-white with appended DTB hasn't booted here since v3.7.
> And the BeagleBone-black with discrete DTB doesn't boot at all with
> current mainline, only with the TI vendor kernel & DTB...
Anyone care to shed light on what's missing for BeagleBone boot with
mainline currently?
I've also not been able to boot a mainline kernel on the BeagleBone for
some time.
Kevin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-06 18:30 ` Santosh Shilimkar
@ 2013-06-07 5:55 ` Sricharan R
2013-06-07 7:52 ` Paul Walmsley
0 siblings, 1 reply; 38+ messages in thread
From: Sricharan R @ 2013-06-07 5:55 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 07 June 2013 12:00 AM, Santosh Shilimkar wrote:
> On Thursday 06 June 2013 01:57 PM, Paul Walmsley wrote:
>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>
>>> From: Sricharan R <r.sricharan@ti.com>
>>>
>>> - The IO resource information like dma request lines, irq number and
>>> ocp address space can be populated via dt blob. So such data is stripped
>>> from OMAP4 SOC hwmod data file.
>>>
>>> - The devices which are still missing the device tree bindings,
>>> address space entries are not removed yet. When such devices add
>>> the dt bindings, respective address space data can be deleted.
>>>
>>> - Also other unnessecary hwmods like firewalls are removed as a part of this.
>>>
>>> The above update, results in reduction of about ~1650 lines of code.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Signed-off-by: Sricharan R <r.sricharan@ti.com>
>> I assume that you're not autogenerating this data any more, based on
>> your change list above. If that's correct, please also remove
>> the paragraph at the top of the file:
>>
> The data is auto-generated. I let Sricharan comment if it is otherwise
> in the final version of the patch.
>
> Sricharan ?
I used autogen to remove the data, but some of the data were not in sync
with the mainline .(like abe, dss, aess, context register offsets etc..).
So i have to sync them manually.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-07 5:55 ` Sricharan R
@ 2013-06-07 7:52 ` Paul Walmsley
2013-06-07 9:01 ` Sricharan R
0 siblings, 1 reply; 38+ messages in thread
From: Paul Walmsley @ 2013-06-07 7:52 UTC (permalink / raw)
To: linux-arm-kernel
cc Beno?t
On Fri, 7 Jun 2013, Sricharan R wrote:
> I used autogen to remove the data, but some of the data were not in sync
> with the mainline .(like abe, dss, aess, context register offsets etc..).
> So i have to sync them manually.
OK. Are you going to fix the differences up soon?
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-07 7:52 ` Paul Walmsley
@ 2013-06-07 9:01 ` Sricharan R
2013-06-07 9:46 ` Tero Kristo
0 siblings, 1 reply; 38+ messages in thread
From: Sricharan R @ 2013-06-07 9:01 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 07 June 2013 01:22 PM, Paul Walmsley wrote:
> cc Beno?t
>
> On Fri, 7 Jun 2013, Sricharan R wrote:
>
>> I used autogen to remove the data, but some of the data were not in sync
>> with the mainline .(like abe, dss, aess, context register offsets etc..).
>> So i have to sync them manually.
> OK. Are you going to fix the differences up soon?
>
> - Paul
+ Ambresh and Tero for autogen.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-07 9:01 ` Sricharan R
@ 2013-06-07 9:46 ` Tero Kristo
2013-06-07 9:50 ` Paul Walmsley
0 siblings, 1 reply; 38+ messages in thread
From: Tero Kristo @ 2013-06-07 9:46 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2013-06-07 at 14:31 +0530, Sricharan R wrote:
> On Friday 07 June 2013 01:22 PM, Paul Walmsley wrote:
> > cc Beno?t
> >
> > On Fri, 7 Jun 2013, Sricharan R wrote:
> >
> >> I used autogen to remove the data, but some of the data were not in sync
> >> with the mainline .(like abe, dss, aess, context register offsets etc..).
> >> So i have to sync them manually.
> > OK. Are you going to fix the differences up soon?
> >
> > - Paul
> + Ambresh and Tero for autogen.
This is not going to happen soon, if ever. We might consider doing this
if a complete overhaul for the hwmod data is going to be done at some
point so that re-generating the new format is easier.
-Tero
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-07 9:46 ` Tero Kristo
@ 2013-06-07 9:50 ` Paul Walmsley
2013-06-07 9:53 ` Sricharan R
0 siblings, 1 reply; 38+ messages in thread
From: Paul Walmsley @ 2013-06-07 9:50 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 7 Jun 2013, Tero Kristo wrote:
> On Fri, 2013-06-07 at 14:31 +0530, Sricharan R wrote:
> > On Friday 07 June 2013 01:22 PM, Paul Walmsley wrote:
> > > cc Beno?t
> > >
> > > On Fri, 7 Jun 2013, Sricharan R wrote:
> > >
> > >> I used autogen to remove the data, but some of the data were not in sync
> > >> with the mainline .(like abe, dss, aess, context register offsets etc..).
> > >> So i have to sync them manually.
> > > OK. Are you going to fix the differences up soon?
> > >
> > > - Paul
> > + Ambresh and Tero for autogen.
>
> This is not going to happen soon, if ever. We might consider doing this
> if a complete overhaul for the hwmod data is going to be done at some
> point so that re-generating the new format is easier.
OK. Sricharan, how about reposting the OMAP4 hwmod data patch and drop
the comment regarding autogeneration? That will be more accurate and will
save some more lines.
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file
2013-06-07 9:50 ` Paul Walmsley
@ 2013-06-07 9:53 ` Sricharan R
0 siblings, 0 replies; 38+ messages in thread
From: Sricharan R @ 2013-06-07 9:53 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 07 June 2013 03:20 PM, Paul Walmsley wrote:
> On Fri, 7 Jun 2013, Tero Kristo wrote:
>
>> On Fri, 2013-06-07 at 14:31 +0530, Sricharan R wrote:
>>> On Friday 07 June 2013 01:22 PM, Paul Walmsley wrote:
>>>> cc Beno?t
>>>>
>>>> On Fri, 7 Jun 2013, Sricharan R wrote:
>>>>
>>>>> I used autogen to remove the data, but some of the data were not in sync
>>>>> with the mainline .(like abe, dss, aess, context register offsets etc..).
>>>>> So i have to sync them manually.
>>>> OK. Are you going to fix the differences up soon?
>>>>
>>>> - Paul
>>> + Ambresh and Tero for autogen.
>> This is not going to happen soon, if ever. We might consider doing this
>> if a complete overhaul for the hwmod data is going to be done at some
>> point so that re-generating the new format is easier.
> OK. Sricharan, how about reposting the OMAP4 hwmod data patch and drop
> the comment regarding autogeneration? That will be more accurate and will
> save some more lines.
>
>
> - Paul
ok, sure, i will repost by dropping that comment.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-06 4:00 ` Paul Walmsley
2013-06-06 22:27 ` Kevin Hilman
@ 2013-06-07 16:13 ` Tony Lindgren
1 sibling, 0 replies; 38+ messages in thread
From: Tony Lindgren @ 2013-06-07 16:13 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [130605 21:06]:
> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > AM33XX only supports DT boot mode and with addition of
> > extracting module resources like, irq, dma and address space
> > from DT block, so now we can remove duplicate information from
> > hwmod data file.
>
> OK, guess I'll take your word for it that it all works. The
> BeagleBone-white with appended DTB hasn't booted here since v3.7.
> And the BeagleBone-black with discrete DTB doesn't boot at all with
> current mainline, only with the TI vendor kernel & DTB...
>
> Acked-by: Paul Walmsley <paul@pwsan.com>
Thanks applying into omap-for-v3.11/cleanup.
Regards,
Tony
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-06 22:27 ` Kevin Hilman
@ 2013-06-07 17:01 ` Santosh Shilimkar
2013-06-10 8:35 ` Lokesh Vutla
2013-06-12 6:04 ` Hiremath, Vaibhav
2 siblings, 0 replies; 38+ messages in thread
From: Santosh Shilimkar @ 2013-06-07 17:01 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 06 June 2013 06:27 PM, Kevin Hilman wrote:
> Paul Walmsley <paul@pwsan.com> writes:
>
>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>
>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>> AM33XX only supports DT boot mode and with addition of
>>> extracting module resources like, irq, dma and address space
>>> from DT block, so now we can remove duplicate information from
>>> hwmod data file.
>>
>> OK, guess I'll take your word for it that it all works. The
>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
>> And the BeagleBone-black with discrete DTB doesn't boot at all with
>> current mainline, only with the TI vendor kernel & DTB...
>
> Anyone care to shed light on what's missing for BeagleBone boot with
> mainline currently?
>
> I've also not been able to boot a mainline kernel on the BeagleBone for
> some time.
>
Looping Rajendra.
Regards,
Santosh
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 03/14] ARM: OMAP4+: CM: Move function prototypes to common header for re-use
2013-05-29 16:38 ` [PATCH 03/14] ARM: OMAP4+: CM: " Santosh Shilimkar
@ 2013-06-08 17:44 ` Paul Walmsley
0 siblings, 0 replies; 38+ messages in thread
From: Paul Walmsley @ 2013-06-08 17:44 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 29 May 2013, Santosh Shilimkar wrote:
> OMAP5 reuses OMAP4 CM IP block which lets us re-use CM1/CM2 functions.
> So move the function prototypes from cm1_44xx.h, cm2_44xx.h to
> cm_prm44xx_54xx.h header. The suggestion came from Paul Walmsley
> as part of the OMAP5 data file review.
>
> This is preparatory patch to add OMAP5 CM data file.
>
> Cc: Paul Walmsley <paul@pwsan.com>
...
> new file mode 100644
> index 0000000..4154f86
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
> @@ -0,0 +1,36 @@
> +/*
> + * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
> + *
> + * Copyright (C) 2009-201333 Texas Instruments, Inc.
Heh, looks like someone's a vi user ;-)
Fixed in the local copy here.
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 04/14] ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
[not found] ` <1369845494-30231-5-git-send-email-santosh.shilimkar@ti.com>
@ 2013-06-08 17:54 ` Paul Walmsley
0 siblings, 0 replies; 38+ messages in thread
From: Paul Walmsley @ 2013-06-08 17:54 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 29 May 2013, Santosh Shilimkar wrote:
> From: Benoit Cousson <b-cousson@ti.com>
>
> Add the new defines for OMAP54XX cm registers.
>
> Cc: Paul Walmsley <paul@pwsan.com>
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> [santosh.shilimkar at ti.com: Generated es2.0 data]
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
...
> diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
> new file mode 100644
> index 0000000..7b1f3b6
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cm1_54xx.h
...
> +
> +/* Function prototypes */
> +extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
> +extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
> +extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
No need for these since they're already prototyped in a common
file in your earlier patch set.
> diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
> new file mode 100644
> index 0000000..bab76bd
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cm2_54xx.h
> @@ -0,0 +1,394 @@
...
> +/* Function prototypes */
> +extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
> +extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
> +extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
No need for these since they're already prototyped in a common
file in your earlier patch set.
Fixed in the local copy here.
- Paul
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-06 22:27 ` Kevin Hilman
2013-06-07 17:01 ` Santosh Shilimkar
@ 2013-06-10 8:35 ` Lokesh Vutla
2013-06-10 12:43 ` Lokesh Vutla
2013-06-10 17:03 ` Kevin Hilman
2013-06-12 6:04 ` Hiremath, Vaibhav
2 siblings, 2 replies; 38+ messages in thread
From: Lokesh Vutla @ 2013-06-10 8:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kevin,
On Friday 07 June 2013 03:57 AM, Kevin Hilman wrote:
> Paul Walmsley <paul@pwsan.com> writes:
>
>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>
>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>> AM33XX only supports DT boot mode and with addition of
>>> extracting module resources like, irq, dma and address space
>>> from DT block, so now we can remove duplicate information from
>>> hwmod data file.
>>
>> OK, guess I'll take your word for it that it all works. The
>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
>> And the BeagleBone-black with discrete DTB doesn't boot at all with
>> current mainline, only with the TI vendor kernel & DTB...
>
> Anyone care to shed light on what's missing for BeagleBone boot with
> mainline currently?
I have tested BeagleBone boot with today's mainline bootloader and
kernel. It boots perfectly fine.
Thanks and regards,
Lokesh
>
> I've also not been able to boot a mainline kernel on the BeagleBone for
> some time.
>
> Kevin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-10 8:35 ` Lokesh Vutla
@ 2013-06-10 12:43 ` Lokesh Vutla
2013-06-10 17:03 ` Kevin Hilman
1 sibling, 0 replies; 38+ messages in thread
From: Lokesh Vutla @ 2013-06-10 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
On Monday 10 June 2013 02:05 PM, Lokesh Vutla wrote:
> Hi Kevin,
>
> On Friday 07 June 2013 03:57 AM, Kevin Hilman wrote:
>> Paul Walmsley <paul@pwsan.com> writes:
>>
>>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>>
>>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>>
>>>> AM33XX only supports DT boot mode and with addition of
>>>> extracting module resources like, irq, dma and address space
>>>> from DT block, so now we can remove duplicate information from
>>>> hwmod data file.
>>>
>>> OK, guess I'll take your word for it that it all works. The
>>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
>>> And the BeagleBone-black with discrete DTB doesn't boot at all with
>>> current mainline, only with the TI vendor kernel & DTB...
>>
>> Anyone care to shed light on what's missing for BeagleBone boot with
>> mainline currently?
> I have tested BeagleBone boot with today's mainline bootloader and
> kernel. It boots perfectly fine.
I have taken the boot log for BeagleBone from the folllowing site:
http://www.pwsan.com/omap/testlogs/test_v3.10-rc5/20130609031534/boot/am335xbone/
I have reset to your U-Boot commit id and took latest mainline kernel.
It boots fine in my setup.
You can find the logs here: http://pastebin.com/ggVYs3RG
Thanks and regards,
Lokesh
>
> Thanks and regards,
> Lokesh
>>
>> I've also not been able to boot a mainline kernel on the BeagleBone for
>> some time.
>>
>> Kevin
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-10 8:35 ` Lokesh Vutla
2013-06-10 12:43 ` Lokesh Vutla
@ 2013-06-10 17:03 ` Kevin Hilman
2013-06-11 4:14 ` Lokesh Vutla
1 sibling, 1 reply; 38+ messages in thread
From: Kevin Hilman @ 2013-06-10 17:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi Lokesh,
Lokesh Vutla <lokeshvutla@ti.com> writes:
> Hi Kevin,
>
> On Friday 07 June 2013 03:57 AM, Kevin Hilman wrote:
>> Paul Walmsley <paul@pwsan.com> writes:
>>
>>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>>
>>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>>
>>>> AM33XX only supports DT boot mode and with addition of
>>>> extracting module resources like, irq, dma and address space
>>>> from DT block, so now we can remove duplicate information from
>>>> hwmod data file.
>>>
>>> OK, guess I'll take your word for it that it all works. The
>>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
>>> And the BeagleBone-black with discrete DTB doesn't boot at all with
>>> current mainline, only with the TI vendor kernel & DTB...
>>
>> Anyone care to shed light on what's missing for BeagleBone boot with
>> mainline currently?
> I have tested BeagleBone boot with today's mainline bootloader and
> kernel. It boots perfectly fine.
Can you post git trees + branch names (and/or commit IDs) and also
kernel config please?
Thanks,
Kevin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-10 17:03 ` Kevin Hilman
@ 2013-06-11 4:14 ` Lokesh Vutla
2013-06-12 6:00 ` Hiremath, Vaibhav
0 siblings, 1 reply; 38+ messages in thread
From: Lokesh Vutla @ 2013-06-11 4:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kevin,
On Monday 10 June 2013 10:33 PM, Kevin Hilman wrote:
> Hi Lokesh,
>
> Lokesh Vutla <lokeshvutla@ti.com> writes:
>
>> Hi Kevin,
>>
>> On Friday 07 June 2013 03:57 AM, Kevin Hilman wrote:
>>> Paul Walmsley <paul@pwsan.com> writes:
>>>
>>>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
>>>>
>>>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>>>
>>>>> AM33XX only supports DT boot mode and with addition of
>>>>> extracting module resources like, irq, dma and address space
>>>>> from DT block, so now we can remove duplicate information from
>>>>> hwmod data file.
>>>>
>>>> OK, guess I'll take your word for it that it all works. The
>>>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
>>>> And the BeagleBone-black with discrete DTB doesn't boot at all with
>>>> current mainline, only with the TI vendor kernel & DTB...
>>>
>>> Anyone care to shed light on what's missing for BeagleBone boot with
>>> mainline currently?
>> I have tested BeagleBone boot with today's mainline bootloader and
>> kernel. It boots perfectly fine.
>
> Can you post git trees + branch names (and/or commit IDs) and also
> kernel config please?
Following are the details:
U-Boot:
url: git://git.denx.de/u-boot.git
branch : master
config: am335x_evm
Top commit: "842033e pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option"
Kernel:
url: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
branch: master
config: omap2plus_defocnfig
dtb file: am335x-bone.dtb
Top commit: "317ddd2 Linux 3.10-rc5" (On top of this I have a local
patch for appending dtb)
You can find the logs here: http://pastebin.com/vcBr0UhM
Thanks and regards,
Lokesh
>
> Thanks,
>
> Kevin
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-11 4:14 ` Lokesh Vutla
@ 2013-06-12 6:00 ` Hiremath, Vaibhav
2013-06-12 22:39 ` Kevin Hilman
0 siblings, 1 reply; 38+ messages in thread
From: Hiremath, Vaibhav @ 2013-06-12 6:00 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Vutla, Lokesh
> Sent: Tuesday, June 11, 2013 9:45 AM
> To: Kevin Hilman
> Cc: Paul Walmsley; Shilimkar, Santosh; tony at atomide.com; linux-arm-
> kernel at lists.infradead.org; linux-omap at vger.kernel.org; Hiremath,
> Vaibhav; R, Sricharan; Nayak, Rajendra
> Subject: Re: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr
> info clean up
>
> Hi Kevin,
> On Monday 10 June 2013 10:33 PM, Kevin Hilman wrote:
> > Hi Lokesh,
> >
> > Lokesh Vutla <lokeshvutla@ti.com> writes:
> >
> >> Hi Kevin,
> >>
> >> On Friday 07 June 2013 03:57 AM, Kevin Hilman wrote:
> >>> Paul Walmsley <paul@pwsan.com> writes:
> >>>
> >>>> On Wed, 29 May 2013, Santosh Shilimkar wrote:
> >>>>
> >>>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
> >>>>>
> >>>>> AM33XX only supports DT boot mode and with addition of
> >>>>> extracting module resources like, irq, dma and address space
> >>>>> from DT block, so now we can remove duplicate information from
> >>>>> hwmod data file.
> >>>>
> >>>> OK, guess I'll take your word for it that it all works. The
> >>>> BeagleBone-white with appended DTB hasn't booted here since v3.7.
> >>>> And the BeagleBone-black with discrete DTB doesn't boot at all
> with
> >>>> current mainline, only with the TI vendor kernel & DTB...
> >>>
> >>> Anyone care to shed light on what's missing for BeagleBone boot
> with
> >>> mainline currently?
> >> I have tested BeagleBone boot with today's mainline bootloader and
> >> kernel. It boots perfectly fine.
> >
> > Can you post git trees + branch names (and/or commit IDs) and also
> > kernel config please?
> Following are the details:
> U-Boot:
> url: git://git.denx.de/u-boot.git
> branch : master
> config: am335x_evm
> Top commit: "842033e pci: introduce CONFIG_PCI_INDIRECT_BRIDGE
> option"
>
> Kernel:
> url:
> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-
> 2.6.git
> branch: master
> config: omap2plus_defocnfig
> dtb file: am335x-bone.dtb
> Top commit: "317ddd2 Linux 3.10-rc5" (On top of this I have a local
> patch for appending dtb)
> You can find the logs here: http://pastebin.com/vcBr0UhM
>
Paul/Kevin/Santosh,
AM335x is booting up from Mainline, starting from v3.7, that?s where HWMOD data got merged to
Mainline.
We have discussed on this in the past as well, let me explain the issue here in detail
again for everybody -
In case of Am335x we have only two possible options, as AM335x only boots up
With DTB (Tested in BBB) -
1. Mainline u-boot + mainline Kernel:
=====================================
1.a. Appended DTB method
------------------------
Here you __must__ enabled below config options in order to get kernel booting,
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
And, I have used below command to append DTB to kernel image
# cat arch/arm/boot/zImage arch/arm/boot/dts/am335x-bone.dtb > zImage-append && mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 -n "Linux" -d zImage-append uImage-append
I have attached complete log here with this mail for reference
http://pastebin.com/82duFh78
1.b. Discrete DTB and uImage method:
------------------------------------
Here you don?t need to enable any extra config options. Plain omap2plus_defconfig
Should work without any issues.
I have attached complete log here with this mail for reference
http://pastebin.com/Nqr0PiwW
2. Older U-Boot (without DTB) + Mainline Kernel:
================================================
This is same as #OPTION-1.a above.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-06 22:27 ` Kevin Hilman
2013-06-07 17:01 ` Santosh Shilimkar
2013-06-10 8:35 ` Lokesh Vutla
@ 2013-06-12 6:04 ` Hiremath, Vaibhav
2013-06-12 6:26 ` Hiremath, Vaibhav
2 siblings, 1 reply; 38+ messages in thread
From: Hiremath, Vaibhav @ 2013-06-12 6:04 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at linaro.org]
> Sent: Friday, June 07, 2013 3:57 AM
> To: Paul Walmsley
> Cc: Shilimkar, Santosh; tony at atomide.com; linux-arm-
> kernel at lists.infradead.org; linux-omap at vger.kernel.org; Hiremath,
> Vaibhav; R, Sricharan
> Subject: Re: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr
> info clean up
>
> Paul Walmsley <paul@pwsan.com> writes:
>
> > On Wed, 29 May 2013, Santosh Shilimkar wrote:
> >
> >> From: Vaibhav Hiremath <hvaibhav@ti.com>
> >>
> >> AM33XX only supports DT boot mode and with addition of
> >> extracting module resources like, irq, dma and address space
> >> from DT block, so now we can remove duplicate information from
> >> hwmod data file.
> >
> > OK, guess I'll take your word for it that it all works. The
> > BeagleBone-white with appended DTB hasn't booted here since v3.7.
> > And the BeagleBone-black with discrete DTB doesn't boot at all with
> > current mainline, only with the TI vendor kernel & DTB...
>
> Anyone care to shed light on what's missing for BeagleBone boot with
> mainline currently?
>
> I've also not been able to boot a mainline kernel on the BeagleBone for
> some time.
>
Sorry for delayed response, as I was on vacation for almost for a week.
I have just responded to this thread on complete analysis of the issue.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg90309.html
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-12 6:04 ` Hiremath, Vaibhav
@ 2013-06-12 6:26 ` Hiremath, Vaibhav
0 siblings, 0 replies; 38+ messages in thread
From: Hiremath, Vaibhav @ 2013-06-12 6:26 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Hiremath, Vaibhav
> Sent: Wednesday, June 12, 2013 11:34 AM
> To: Kevin Hilman; Paul Walmsley
> Cc: Shilimkar, Santosh; tony at atomide.com; linux-arm-
> kernel at lists.infradead.org; linux-omap at vger.kernel.org; R, Sricharan
> Subject: RE: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr
> info clean up
>
>
> > -----Original Message-----
> > From: Kevin Hilman [mailto:khilman at linaro.org]
> > Sent: Friday, June 07, 2013 3:57 AM
> > To: Paul Walmsley
> > Cc: Shilimkar, Santosh; tony at atomide.com; linux-arm-
> > kernel at lists.infradead.org; linux-omap at vger.kernel.org; Hiremath,
> > Vaibhav; R, Sricharan
> > Subject: Re: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr
> > info clean up
> >
> > Paul Walmsley <paul@pwsan.com> writes:
> >
> > > On Wed, 29 May 2013, Santosh Shilimkar wrote:
> > >
> > >> From: Vaibhav Hiremath <hvaibhav@ti.com>
> > >>
> > >> AM33XX only supports DT boot mode and with addition of
> > >> extracting module resources like, irq, dma and address space
> > >> from DT block, so now we can remove duplicate information from
> > >> hwmod data file.
> > >
> > > OK, guess I'll take your word for it that it all works. The
> > > BeagleBone-white with appended DTB hasn't booted here since v3.7.
> > > And the BeagleBone-black with discrete DTB doesn't boot at all with
> > > current mainline, only with the TI vendor kernel & DTB...
> >
> > Anyone care to shed light on what's missing for BeagleBone boot with
> > mainline currently?
> >
> > I've also not been able to boot a mainline kernel on the BeagleBone
> for
> > some time.
> >
>
> Sorry for delayed response, as I was on vacation for almost for a week.
>
> I have just responded to this thread on complete analysis of the issue.
>
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg90309.html
>
I have also pushed the branch to github,
https://github.com/hvaibhav/am335x-linux.git linus-master
OR
https://github.com/hvaibhav/am335x-linux/tree/linus-master
NOTE: Tested on BeagleBone-Black platform.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-12 6:00 ` Hiremath, Vaibhav
@ 2013-06-12 22:39 ` Kevin Hilman
2013-06-13 4:46 ` Hiremath, Vaibhav
0 siblings, 1 reply; 38+ messages in thread
From: Kevin Hilman @ 2013-06-12 22:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi Vaibhav,
"Hiremath, Vaibhav" <hvaibhav@ti.com> writes:
[...]
> Paul/Kevin/Santosh,
>
> AM335x is booting up from Mainline, starting from v3.7, that?s where HWMOD data got merged to
> Mainline.
>
> We have discussed on this in the past as well, let me explain the issue here in detail
> again for everybody -
Thanks for the detail.
In my case, after more debug, it appears that where I was putting the
DTB in memory from u-boot was not working. Using the addresses you
used gets things working again. Thanks.
u-boot mainline (v2013.04) for BeagleBone has defaults that don't work
appear together:
U-Boot# printenv loadaddr
loadaddr=0x80200000
U-Boot# printenv fdtaddr
fdtaddr=0x80F80000
Changing fdtaddr around got things working again. It's probably a good
idea to change the u-boot defaults to values that work, since that's a
likely starting point for people.
I'm now back to mainline booting well on both my original BeagleBone and
my BeagleBone black.
Thanks,
Kevin
> In case of Am335x we have only two possible options, as AM335x only boots up
> With DTB (Tested in BBB) -
>
> 1. Mainline u-boot + mainline Kernel:
> =====================================
>
> 1.a. Appended DTB method
> ------------------------
>
> Here you __must__ enabled below config options in order to get kernel booting,
>
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
>
> And, I have used below command to append DTB to kernel image
>
> # cat arch/arm/boot/zImage arch/arm/boot/dts/am335x-bone.dtb >
> zImage-append && mkimage -A arm -O linux -T kernel -C none -a
> 0x80008000 -e 0x80008000 -n "Linux" -d zImage-append uImage-append
>
>
> I have attached complete log here with this mail for reference
> http://pastebin.com/82duFh78
>
>
> 1.b. Discrete DTB and uImage method:
> ------------------------------------
>
> Here you don?t need to enable any extra config options. Plain omap2plus_defconfig
> Should work without any issues.
>
> I have attached complete log here with this mail for reference
> http://pastebin.com/Nqr0PiwW
>
>
> 2. Older U-Boot (without DTB) + Mainline Kernel:
> ================================================
>
> This is same as #OPTION-1.a above.
>
>
> Thanks,
> Vaibhav
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up
2013-06-12 22:39 ` Kevin Hilman
@ 2013-06-13 4:46 ` Hiremath, Vaibhav
0 siblings, 0 replies; 38+ messages in thread
From: Hiremath, Vaibhav @ 2013-06-13 4:46 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at linaro.org]
> Sent: Thursday, June 13, 2013 4:09 AM
> To: Hiremath, Vaibhav
> Cc: Vutla, Lokesh; Paul Walmsley; Shilimkar, Santosh; tony at atomide.com;
> linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org; R,
> Sricharan; Nayak, Rajendra
> Subject: Re: [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr
> info clean up
>
> Hi Vaibhav,
>
> "Hiremath, Vaibhav" <hvaibhav@ti.com> writes:
>
> [...]
>
> > Paul/Kevin/Santosh,
> >
> > AM335x is booting up from Mainline, starting from v3.7, that?s where
> HWMOD data got merged to
> > Mainline.
> >
> > We have discussed on this in the past as well, let me explain the
> issue here in detail
> > again for everybody -
>
> Thanks for the detail.
>
> In my case, after more debug, it appears that where I was putting the
> DTB in memory from u-boot was not working. Using the addresses you
> used gets things working again. Thanks.
>
> u-boot mainline (v2013.04) for BeagleBone has defaults that don't work
> appear together:
>
> U-Boot# printenv loadaddr
> loadaddr=0x80200000
> U-Boot# printenv fdtaddr
> fdtaddr=0x80F80000
>
I tried above address and it is booting up for me, below is the log for your reference -
Boot LOG:
=========================================
U-Boot SPL 2013.04-00274-ga71d45d (Jun 12 2013 - 10:54:45)
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401800 using PIO, IRQ 0
OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img
U-Boot 2013.04-00274-ga71d45d (Jun 12 2013 - 10:54:45)
I2C: ready
DRAM: 512 MiB
WARNING: Caches not enabled
NAND: No NAND device found!!!
0 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - readenv() failed, using default environment
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401800 using PIO, IRQ 0
Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 0
U-Boot#
U-Boot#
U-Boot#
U-Boot#
U-Boot#
U-Boot#
U-Boot# mmc rescan
U-Boot# fatload mmc 0 0x80F80000 am335x-bone.dtb
reading am335x-bone.dtb
8865 bytes read in 6 ms (1.4 MiB/s)
U-Boot# fatload mmc 0 0x80200000 uImage
reading uImage
4044224 bytes read in 464 ms (8.3 MiB/s)
U-Boot# fatload mmc 0 82000000 ramdisk-pm.gz
reading ramdisk-pm.gz
2022580 bytes read in 235 ms (8.2 MiB/s)
U-Boot# setenv bootargs console=ttyO0,115200n8 mem=256M root=/dev/ram rw initrd=0x82000000,32MB ramdisk_size=65536 earlyprintk=serial omap_wdt.nowayout=60
U-Boot# bootm 0x80200000 - 0x80F80000
## Booting kernel from Legacy Image at 80200000 ...
Image Name: Linux-3.10.0-rc5-00054-g75da4e1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4044160 Bytes = 3.9 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 80f80000
Booting using the fdt blob at 0x80f80000
Loading Kernel Image ... OK
OK
Using Device Tree in place at 80f80000, end 80f852a0
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.10.0-rc5-00054-g75da4e1 (a0393758 at psplinux064) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #1 SMP Wed Jun 12 10:51:03 IST 2013
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: Generic AM33XX (Flattened Device Tree), model: TI AM335x BeagleBone
[ 0.000000] cma: CMA: reserved 16 MiB at 8e800000
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] AM335X ES2.0 (neon )
[ 0.000000] PERCPU: Embedded 9 pages/cpu @c0f83000 s13632 r8192 d15040 u36864
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64768
[ 0.000000] Kernel command line: console=ttyO0,115200n8 mem=256M root=/dev/ram rw initrd=0x82000000,32MB ramdisk_size=65536 earlyprintk=serial omap_wdt.nowayout=60
[ 0.000000] Booting kernel: `60' invalid for parameter `omap_wdt.nowayout'
[ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Memory: 255MB = 255MB total
[ 0.000000] Memory: 195812k/195812k available, 66332k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xd0800000 - 0xff000000 ( 744 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xd0000000 ( 256 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0717e40 (7232 kB)
[ 0.000000] .init : 0xc0718000 - 0xc077a540 ( 394 kB)
[ 0.000000] .data : 0xc077c000 - 0xc0812748 ( 602 kB)
[ 0.000000] .bss : 0xc0812748 - 0xc0d76b98 (5522 kB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
[ 0.000000] Total of 128 interrupts on 1 active controller
[ 0.000000] OMAP clockevent source: timer2 at 24000000 Hz
[ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
[ 0.000000] OMAP clocksource: timer1 at 24000000 Hz
[ 0.000000] Console: colour dummy device 80x30
[ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.000000] ... MAX_LOCK_DEPTH: 48
[ 0.000000] ... MAX_LOCKDEP_KEYS: 8191
[ 0.000000] ... CLASSHASH_SIZE: 4096
[ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.000000] ... CHAINHASH_SIZE: 16384
[ 0.000000] memory used by lock dependency info: 3695 kB
[ 0.000000] per task-struct memory footprint: 1152 bytes
[ 0.001358] Calibrating delay loop... 363.72 BogoMIPS (lpj=1818624)
[ 0.119593] pid_max: default: 32768 minimum: 301
[ 0.120264] Security Framework initialized
[ 0.120460] Mount-cache hash table entries: 512
[ 0.134531] CPU: Testing write buffer coherency: ok
[ 0.136519] CPU0: thread -1, cpu 0, socket -1, mpidr 0
[ 0.136607] Setting up static identity map for 0xc0504ff8 - 0xc0505068
[ 0.140793] Brought up 1 CPUs
[ 0.140823] SMP: Total of 1 processors activated (363.72 BogoMIPS).
[ 0.140838] CPU: All CPU(s) started in SVC mode.
[ 0.145003] devtmpfs: initialized
[ 0.166693] omap_hwmod: debugss: _wait_target_disable failed
[ 0.230142] pinctrl core: initialized pinctrl subsystem
[ 0.236351] regulator-dummy: no parameters
[ 0.241091] NET: Registered protocol family 16
[ 0.251936] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.282410] OMAP GPIO hardware version 0.1
[ 0.312014] No ATAGs?
[ 0.312046] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.398189] bio: create slab <bio-0> at 0
[ 0.412467] SCSI subsystem initialized
[ 0.415411] usbcore: registered new interface driver usbfs
[ 0.416049] usbcore: registered new interface driver hub
[ 0.417035] usbcore: registered new device driver usb
[ 0.419839] omap_i2c 44e0b000.i2c: could not find pctldev for node /pinmux at 44e10800/pinmux_i2c0_pins, deferring probe
[ 0.419903] platform 44e0b000.i2c: Driver omap_i2c requests probe deferral
[ 0.430813] Switching to clocksource timer1
[ 0.619592] NET: Registered protocol family 2
[ 0.622548] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 0.622830] TCP bind hash table entries: 2048 (order: 4, 73728 bytes)
[ 0.624078] TCP: Hash tables configured (established 2048 bind 2048)
[ 0.624356] TCP: reno registered
[ 0.624402] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 0.624748] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 0.626623] NET: Registered protocol family 1
[ 0.629144] RPC: Registered named UNIX socket transport module.
[ 0.629176] RPC: Registered udp transport module.
[ 0.629192] RPC: Registered tcp transport module.
[ 0.629209] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.630501] Trying to unpack rootfs image as initramfs...
[ 0.633407] rootfs image is not initramfs (no cpio magic); looks like an initrd
[ 0.929698] Freeing initrd memory: 32768K (c2000000 - c4000000)
[ 0.929929] NetWinder Floating Point Emulator V0.97 (double precision)
[ 1.191112] VFS: Disk quotas dquot_6.5.2
[ 1.191622] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 1.195187] NFS: Registering the id_resolver key type
[ 1.195835] Key type id_resolver registered
[ 1.195867] Key type id_legacy registered
[ 1.196055] jffs2: version 2.2. (NAND) (SUMMARY) ? 2001-2006 Red Hat, Inc.
[ 1.196790] msgmni has been set to 478
[ 1.201528] io scheduler noop registered
[ 1.201559] io scheduler deadline registered
[ 1.201659] io scheduler cfq registered (default)
[ 1.203470] pinctrl-single 44e10800.pinmux: 142 pins at pa f9e10800 size 568
[ 1.209102] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.219674] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 88) is a OMAP UART0
[ 1.834393] console [ttyO0] enabled
[ 1.882450] brd: module loaded
[ 1.910319] loop: module loaded
[ 1.921131] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.939745] usbcore: registered new interface driver asix
[ 1.946692] usbcore: registered new interface driver ax88179_178a
[ 1.954307] usbcore: registered new interface driver cdc_ether
[ 1.961165] usbcore: registered new interface driver smsc95xx
[ 1.967981] usbcore: registered new interface driver net1080
[ 1.974853] usbcore: registered new interface driver cdc_subset
[ 1.981820] usbcore: registered new interface driver zaurus
[ 1.988373] usbcore: registered new interface driver cdc_ncm
[ 1.997216] usbcore: registered new interface driver cdc_wdm
[ 2.004100] usbcore: registered new interface driver usb-storage
[ 2.011102] usbcore: registered new interface driver usbtest
[ 2.020244] mousedev: PS/2 mouse device common for all mice
[ 2.034865] omap_rtc 44e3e000.rtc: rtc core: registered 44e3e000.rtc as rtc0
[ 2.043174] 44e3e000.rtc: already running
[ 2.049525] i2c /dev entries driver
[ 2.054310] Driver for 1-wire Dallas network protocol.
[ 2.065743] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[ 2.085316] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.094003] usbcore: registered new interface driver usbhid
[ 2.099879] usbhid: USB HID core driver
[ 2.106188] oprofile: no performance counters
[ 2.114316] oprofile: using timer interrupt.
[ 2.119754] TCP: cubic registered
[ 2.123467] Initializing XFRM netlink socket
[ 2.128168] NET: Registered protocol family 17
[ 2.133042] NET: Registered protocol family 15
[ 2.138255] Key type dns_resolver registered
[ 2.143036] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[ 2.151220] ThumbEE CPU extension supported.
[ 2.168166] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[ 2.183328] DCDC1: at 1500 mV
[ 2.189549] vdd_mpu: 925 <--> 1325 mV at 1100 mV
[ 2.197934] vdd_core: 925 <--> 1150 mV at 1100 mV
[ 2.205976] LDO1: at 1800 mV
[ 2.212226] LDO2: at 3300 mV
[ 2.218164] LDO3: at 1800 mV
[ 2.224240] LDO4: at 3300 mV
[ 2.230065] tps65217 0-0024: TPS65217 ID 0xe version 1.2
[ 2.301467] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 2.307911] davinci_mdio 4a101000.mdio: detected phy mask fffffffe
[ 2.318069] libphy: 4a101000.mdio: probed
[ 2.322476] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
[ 2.332671] Random MACID = d2:be:d7:26:fb:7e
[ 2.343346] omap_rtc 44e3e000.rtc: setting system clock to 2000-01-01 23:13:33 UTC (946768413)
[ 2.357708] RAMDISK: gzip image found at block 0
[ 2.854280] VFS: Mounted root (ext2 filesystem) on device 1:0.
[ 2.861960] devtmpfs: mounted
[ 2.866023] Freeing unused kernel memory: 392K (c0718000 - c077a000)
mount: mounting none on /var/shm failed: No such file or directory
::
:: Enabling hot-plug : [SUCCESS]
::
::
: Populating /dev : [SUCCESS]
[SUCCESS]
::
::
:: Setting PATH
::
: syslogd : [SUCCESS]
: telnetd : [SUCCESS]
Please press Enter to activate this console.
::
:: Setting shell environment ...
::
: Path
: Aliases
: Touch Screen
::
:: Done
::
[root at arago /]#
[root at arago /]#
[root at arago /]# zcat /proc/config.gz | grep -r ATAG
CONFIG_ATAGS=y
CONFIG_ATAGS_PROC=y
[root at arago /]#
[root at arago /]# zcat /proc/config.gz | grep -r APPEND
# CONFIG_ARM_APPENDED_DTB is not set
[root at arago /]#
[root at arago /]#
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2013-06-13 4:46 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-05-29 16:38 [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 01/14] ARM: OMAP4+: PRM: Move function prototypes to common header for re-use Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 03/14] ARM: OMAP4+: CM: " Santosh Shilimkar
2013-06-08 17:44 ` Paul Walmsley
2013-05-29 16:38 ` [PATCH 05/14] ARM: OMAP4+: PRCM MPU: " Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 06/14] ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 07/14] ARM: OMAP5: SCRM: Add OMAP54XX header file Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 08/14] ARM: OMAP5: clockdomain data: Add OMAP54XX data and update the header Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 09/14] ARM: OMAP5: powerdomain " Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 10/14] ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 11/14] ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 12/14] ARM: OMAP5: Enable build and frameowrk initialisations Santosh Shilimkar
2013-05-29 16:38 ` [PATCH 13/14] ARM: AM33XX: hwmod data: irq, dma and addr info clean up Santosh Shilimkar
2013-06-06 4:00 ` Paul Walmsley
2013-06-06 22:27 ` Kevin Hilman
2013-06-07 17:01 ` Santosh Shilimkar
2013-06-10 8:35 ` Lokesh Vutla
2013-06-10 12:43 ` Lokesh Vutla
2013-06-10 17:03 ` Kevin Hilman
2013-06-11 4:14 ` Lokesh Vutla
2013-06-12 6:00 ` Hiremath, Vaibhav
2013-06-12 22:39 ` Kevin Hilman
2013-06-13 4:46 ` Hiremath, Vaibhav
2013-06-12 6:04 ` Hiremath, Vaibhav
2013-06-12 6:26 ` Hiremath, Vaibhav
2013-06-07 16:13 ` Tony Lindgren
2013-05-29 16:38 ` [PATCH 14/14] ARM: OMAP4: hwmod data: Clean up the data file Santosh Shilimkar
2013-06-06 17:57 ` Paul Walmsley
2013-06-06 18:30 ` Santosh Shilimkar
2013-06-07 5:55 ` Sricharan R
2013-06-07 7:52 ` Paul Walmsley
2013-06-07 9:01 ` Sricharan R
2013-06-07 9:46 ` Tero Kristo
2013-06-07 9:50 ` Paul Walmsley
2013-06-07 9:53 ` Sricharan R
2013-05-30 0:13 ` [PATCH 00/14] ARM: OMAP5: hwmod, prm/cm data files and updates for 3.11 Tony Lindgren
2013-05-30 0:24 ` Tony Lindgren
[not found] ` <1369845494-30231-5-git-send-email-santosh.shilimkar@ti.com>
2013-06-08 17:54 ` [PATCH 04/14] ARM: OMAP5: CM: Add OMAP54XX register and bitfield files Paul Walmsley
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