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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1740128842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=GvIQ8d5TYCzCTqp4FjW1nkQDlwUNWCKgzYX5Dv2bm5E=; b=1s81yxFBfBM6r5o8P7Xc//nNkIUNEmn04A1iCXJM+bKCkKdc0ram9G7uNYN43Z8lWU4v2X FpRM3tkDIFG0psCw== To: Xianwei Zhao via B4 Relay , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Heiner Kallweit Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xianwei Zhao Subject: Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs In-Reply-To: <20250219-irqchip-gpio-a4-a5-v1-2-3c8e44ae42df@amlogic.com> References: <20250219-irqchip-gpio-a4-a5-v1-0-3c8e44ae42df@amlogic.com> <20250219-irqchip-gpio-a4-a5-v1-2-3c8e44ae42df@amlogic.com> Date: Fri, 21 Feb 2025 10:07:21 +0100 Message-ID: <87o6yvhdiu.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250221_010725_939178_4F38F980 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote: > > +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, > + unsigned int type, u32 *channel_hwirq) > +{ > + u32 val = 0; > + unsigned int idx; > + > + idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); > + > + type &= IRQ_TYPE_SENSE_MASK; > + > + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0); > + > + if (type == IRQ_TYPE_EDGE_BOTH) { > + val |= BIT(ctl->params->edge_both_offset + (idx)); > + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, > + BIT(ctl->params->edge_both_offset + (idx)), val); > + return 0; > + } > + > + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) > + val |= BIT(ctl->params->pol_low_offset + idx); > + > + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) > + val |= BIT(ctl->params->edge_single_offset + idx); > + > + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, > + BIT(idx) | BIT(12 + idx), val); > + > + return 0; > +}; This function is a full copy of meson_s4_gpio_irq_set_type() with the only difference of: s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/ Can you please stick that register offset into the parameter structure and use the function for both variants? Thanks, tglx