From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 349D5C4338F for ; Wed, 18 Aug 2021 21:27:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E9C8B6104F for ; Wed, 18 Aug 2021 21:27:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E9C8B6104F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bzQXjOY77ztHdnfRW2l56JUg4KnOU6YzqxHQGIO41Aw=; b=V++/PlIWzXD+/I 4LHDAtfPCE959qkBA5/xZUklevGuw598P0g30yJDtgzoJhiF3xBdi623mS7To8FIlL6khClLhNHkK 7eXtFRXu8XfYMsZj/4G26JD1Up3G+2qxE4qzsWScEeqRt8DxLESx6FmbZH4zHU1OXXagZJVvc2Ai5 3nqkfLKgjKV2/Prxj4tuWdQYjliNvzyrgfF1GQ6kf337+TKZnrbekc2tX8cI1KSu+x1Z4YiXA5Ff0 AS4EesGqojclrqlgKV3ebJjJisvKEmj1C05ClIWVAuUWsbSreBJQnDa/R5uzxguFLNw3eBkAAAP87 KLLcFhgGDIGvgIJFNv/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGT3F-006gw4-J6; Wed, 18 Aug 2021 21:24:47 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mGT3B-006gva-5a for linux-arm-kernel@lists.infradead.org; Wed, 18 Aug 2021 21:24:42 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C04DF610CD; Wed, 18 Aug 2021 21:24:40 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mGT38-005qM1-Jb; Wed, 18 Aug 2021 22:24:38 +0100 Date: Wed, 18 Aug 2021 22:24:38 +0100 Message-ID: <87o89uzbs9.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: Raghavendra Rao Ananta , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Andre Przywara , Eric Auger , Ricardo Koller , kernel-team@android.com, stable@vger.kernel.org Subject: Re: [PATCH] KVM: arm64: vgic: Resample HW pending state on deactivation In-Reply-To: References: <20210818181432.432256-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@google.com, rananta@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, Alexandru.Elisei@arm.com, andre.przywara@arm.com, eric.auger@redhat.com, ricarkol@google.com, kernel-team@android.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210818_142441_296612_BE225CAD X-CRM114-Status: GOOD ( 44.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 18 Aug 2021 20:40:42 +0100, Oliver Upton wrote: > > Hey Marc, > > On Wed, Aug 18, 2021 at 12:05 PM Raghavendra Rao Ananta > wrote: > > > > On Wed, Aug 18, 2021 at 11:14 AM Marc Zyngier wrote: > > > > > > When a mapped level interrupt (a timer, for example) is deactivated > > > by the guest, the corresponding host interrupt is equally deactivated. > > > However, the fate of the pending state still needs to be dealt > > > with in SW. > > > > > > This is specially true when the interrupt was in the active+pending > > > state in the virtual distributor at the point where the guest > > > was entered. On exit, the pending state is potentially stale > > > (the guest may have put the interrupt in a non-pending state). > > > > > > If we don't do anything, the interrupt will be spuriously injected > > > in the guest. Although this shouldn't have any ill effect (spurious > > > interrupts are always possible), we can improve the emulation by > > > detecting the deactivation-while-pending case and resample the > > > interrupt. > > > > > > Fixes: e40cc57bac79 ("KVM: arm/arm64: vgic: Support level-triggered mapped interrupts") > > > Reported-by: Raghavendra Rao Ananta > > > Signed-off-by: Marc Zyngier > > > Cc: stable@vger.kernel.org > > > --- > > > arch/arm64/kvm/vgic/vgic-v2.c | 25 ++++++++++++++++++------- > > > arch/arm64/kvm/vgic/vgic-v3.c | 25 ++++++++++++++++++------- > > > 2 files changed, 36 insertions(+), 14 deletions(-) > > > > > Tested-by: Raghavendra Rao Ananta > > > > Thanks, > > Raghavendra > > > diff --git a/arch/arm64/kvm/vgic/vgic-v2.c b/arch/arm64/kvm/vgic/vgic-v2.c > > > index 2c580204f1dc..3e52ea86a87f 100644 > > > --- a/arch/arm64/kvm/vgic/vgic-v2.c > > > +++ b/arch/arm64/kvm/vgic/vgic-v2.c > > > @@ -60,6 +60,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) > > > u32 val = cpuif->vgic_lr[lr]; > > > u32 cpuid, intid = val & GICH_LR_VIRTUALID; > > > struct vgic_irq *irq; > > > + bool deactivated; > > > > > > /* Extract the source vCPU id from the LR */ > > > cpuid = val & GICH_LR_PHYSID_CPUID; > > > @@ -75,7 +76,8 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) > > > > > > raw_spin_lock(&irq->irq_lock); > > > > > > - /* Always preserve the active bit */ > > > + /* Always preserve the active bit, note deactivation */ > > > + deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT); > > > irq->active = !!(val & GICH_LR_ACTIVE_BIT); > > > > > > if (irq->active && vgic_irq_is_sgi(intid)) > > > @@ -105,6 +107,12 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) > > > * device state could have changed or we simply need to > > > * process the still pending interrupt later. > > > * > > > + * We could also have entered the guest with the interrupt > > > + * active+pending. On the next exit, we need to re-evaluate > > > + * the pending state, as it could otherwise result in a > > > + * spurious interrupt by injecting a now potentially stale > > > + * pending state. > > > + * > > > * If this causes us to lower the level, we have to also clear > > > * the physical active state, since we will otherwise never be > > > * told when the interrupt becomes asserted again. > > > @@ -115,12 +123,15 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) > > > if (vgic_irq_is_mapped_level(irq)) { > > > bool resample = false; > > > > > > - if (val & GICH_LR_PENDING_BIT) { > > > - irq->line_level = vgic_get_phys_line_level(irq); > > > - resample = !irq->line_level; > > > - } else if (vgic_irq_needs_resampling(irq) && > > > - !(irq->active || irq->pending_latch)) { > > > - resample = true; > > > + if (unlikely(vgic_irq_needs_resampling(irq))) { > > > + if (!(irq->active || irq->pending_latch)) > > > + resample = true; > > > + } else { > > > + if ((val & GICH_LR_PENDING_BIT) || > > > + (deactivated && irq->line_level)) { > > > + irq->line_level = vgic_get_phys_line_level(irq); > > > + resample = !irq->line_level; > > > + } > > > } > > > > > > if (resample) > > > diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c > > > index 66004f61cd83..74f9aefffd5e 100644 > > > --- a/arch/arm64/kvm/vgic/vgic-v3.c > > > +++ b/arch/arm64/kvm/vgic/vgic-v3.c > > > @@ -46,6 +46,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) > > > u32 intid, cpuid; > > > struct vgic_irq *irq; > > > bool is_v2_sgi = false; > > > + bool deactivated; > > > > > > cpuid = val & GICH_LR_PHYSID_CPUID; > > > cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; > > > @@ -68,7 +69,8 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) > > > > > > raw_spin_lock(&irq->irq_lock); > > > > > > - /* Always preserve the active bit */ > > > + /* Always preserve the active bit, note deactivation */ > > > + deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT); > > > irq->active = !!(val & ICH_LR_ACTIVE_BIT); > > > > > > if (irq->active && is_v2_sgi) > > > @@ -98,6 +100,12 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) > > > * device state could have changed or we simply need to > > > * process the still pending interrupt later. > > > * > > > + * We could also have entered the guest with the interrupt > > > + * active+pending. On the next exit, we need to re-evaluate > > > + * the pending state, as it could otherwise result in a > > > + * spurious interrupt by injecting a now potentially stale > > > + * pending state. > > > + * > > > * If this causes us to lower the level, we have to also clear > > > * the physical active state, since we will otherwise never be > > > * told when the interrupt becomes asserted again. > > > @@ -108,12 +116,15 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) > > > if (vgic_irq_is_mapped_level(irq)) { > > > bool resample = false; > > > > > > - if (val & ICH_LR_PENDING_BIT) { > > > - irq->line_level = vgic_get_phys_line_level(irq); > > > - resample = !irq->line_level; > > > - } else if (vgic_irq_needs_resampling(irq) && > > > - !(irq->active || irq->pending_latch)) { > > > - resample = true; > > > + if (unlikely(vgic_irq_needs_resampling(irq))) { > > > + if (!(irq->active || irq->pending_latch)) > > > + resample = true; > > > + } else { > > > + if ((val & ICH_LR_PENDING_BIT) || > > > + (deactivated && irq->line_level)) { > > > + irq->line_level = vgic_get_phys_line_level(irq); > > > + resample = !irq->line_level; > > > + } > > The vGICv3 and vGICv2 implementations look identical here, should we > have a helper that keeps the code common between the two? Probably. This code used to be much simpler, but it has grown a bit unwieldy since I added the M1 support hack. This change doesn't make look any better so it is probably time for a minor refactor. I've pushed out an updated patch, but I'll wait a bit more for additional feedback before posting it again. > > Otherwise, the functional change LGTM, so: > > Reviewed-by: Oliver Upton Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel