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Tue, 30 Mar 2021 10:33:23 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRBgU-003PS5-99 for linux-arm-kernel@lists.infradead.org; Tue, 30 Mar 2021 10:33:20 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B5545619AB; Tue, 30 Mar 2021 10:33:16 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lRBgQ-004eeQ-Js; Tue, 30 Mar 2021 11:33:14 +0100 Date: Tue, 30 Mar 2021 11:33:13 +0100 Message-ID: <87o8f1q6c6.wl-maz@kernel.org> From: Marc Zyngier To: Lecopzer Chen Cc: , , , , , Lorenzo Pieralisi , Julien Thierry Subject: Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600 In-Reply-To: <20210330100619.24747-1-lecopzer.chen@mediatek.com> References: <20210330100619.24747-1-lecopzer.chen@mediatek.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: lecopzer.chen@mediatek.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, lecopzer@gmail.com, yj.chiang@mediatek.com, lorenzo.pieralisi@arm.com, julien.thierry.kdev@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_113318_796333_170CB3B0 X-CRM114-Status: GOOD ( 27.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [+Lorenzo, +Julien on an actual email address] On Tue, 30 Mar 2021 11:06:19 +0100, Lecopzer Chen wrote: > > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ > by byte ops, and this doesn't work in GIC-600. > > We have asked ARM Support [1]: > > Please refer to following description in > > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for > > the GIC600 ACE-lite slave interface supported sizes: > > "The GIC-600 only accepts single beat accesses of the sizes for > > each register that are shown in the Programmers model, > > see Chapter 4 Programmer's model on page 4-102. > > All other accesses are rejected and given either an > > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.". > > Thus the register needs to be written by double word operation and > the step will be: read 32bit, set byte and write it back. > > [1] https://services.arm.com/support/s/case/5003t00001L4Pba You do realise that this link: - is unusable for most people as it is behind a registration interface - discloses confidential information to other people I strongly suggest you stop posting such links. > > Signed-off-by: Lecopzer Chen > --- > drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index eb0ee356a629..cfc5a6ad30dc 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio) > { > void __iomem *base = gic_dist_base(d); > u32 offset, index; > + u32 val, prio_offset_mask, prio_offset_shift; > > offset = convert_offset_index(d, GICD_IPRIORITYR, &index); > > - writeb_relaxed(prio, base + offset + index); > + /* > + * GIC-600 memory mapping register doesn't support byte opteration, > + * thus read 32-bits from register, set bytes and wtire back to it. > + */ > + prio_offset_shift = (index & 0x3) * 8; > + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift); > + index &= ~0x3; > + val = readl_relaxed(base + offset + index); > + val &= ~prio_offset_mask; > + val |= prio << prio_offset_shift; > + writel_relaxed(val, base + offset + index); > } > > static u32 gic_get_ppi_index(struct irq_data *d) >From the architecture spec: 11.1.3 GIC memory-mapped register access In any system, access to the following registers must be supported: [...] * Byte accesses to: - GICD_IPRIORITYR. - GICD_ITARGETSR. - GICD_SPENDSGIR. - GICD_CPENDSGIR. - GICR_IPRIORITYR. So if GIC600 doesn't follow this architectural requirement, this is a HW erratum, and I want an actual description of the HW issue together with an erratum number. Lorenzo, can you please investigate on your side? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel