From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A326C3DA49 for ; Sun, 28 Jul 2024 21:54:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Message-ID:Date:References:In-Reply-To:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=B9+cjLHqDZgbaK/4O4LEC/KBl6lBvCQGdqfu4sSl55g=; b=IUYmfFecVE/1E1RmU1c9wAKt9S MacDiDwRh2qfc28yOjm0JzSwf3xxCNpwXHVmDUIoKhRh+5ZyIxT5shjpXnmwmYHvjynpO/KB70RPY SoIuuA0wmon6ljISNvzz41jx4uehUYzI0qXv/thYn2Wofc3A4BXUrANx/mXfqC180A2m9Tp9We0WZ 9OQrPM3ygBng3PoVxI7Yk3rzhQAKYr98I7HzW1bkwp6Cei49nwD0os1WUVvvxsWK2eDLfyFAy7Ja+ k9C37ke98+JRczq6uumZ2p4bZ/07hOMglDG7wp9M6v7m+/ZxTa0IiqrumQdItwRgoSMQchTDa2SmF QsglKI+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYBqR-00000009IaO-0oMY; Sun, 28 Jul 2024 21:54:23 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYBq0-00000009IWD-0BbZ for linux-arm-kernel@lists.infradead.org; Sun, 28 Jul 2024 21:53:59 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722203634; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B9+cjLHqDZgbaK/4O4LEC/KBl6lBvCQGdqfu4sSl55g=; b=gtCaL2M9NA5J3v6zALBBCavEiKes3cGkT+dggJcF9Z9x1q9Ud57eTj5nvtk3Z7UpLUzb48 kFq8jPh6bVUYB8/82WM4L6ljjR2T6uv0CDZPeY7bvpGYzsEfv3mN+c90YjR5OWJ1H/veo3 giaqIvCeJT7wwjnlpF1ZG1A8iYklcYbX1ulvV5oyZTAgC3EwD320LEV4vv3NKRdxTKNocW 97OWCgmXEeA0M06gYgCP00tT2PFaFEkWozHgPPalvf2IAYMtr9VqoryMskj0/rTT+mrtWW 89UvWgHmE0oK65xZi2zDjjJoIh56fVNj4u9K95VOXmjNwTaHzomtnAn74LbpjQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722203634; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B9+cjLHqDZgbaK/4O4LEC/KBl6lBvCQGdqfu4sSl55g=; b=jDCZ09RRi6KNw0dC+4ezeSNhIY2zZxSlViNupqEINr1p+X0IGtTElEy1gEC5J8P+h4KCFs pMYcYUbRxeSHktDw== To: Marek =?utf-8?Q?Beh=C3=BAn?= , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , Ilpo =?utf-8?Q?J=C3=A4rvinen?= Cc: Marek =?utf-8?Q?Beh=C3=BAn?= Subject: Re: [PATCH 11/13] irqchip/armada-370-xp: Iterate only valid bits of the per-CPU interrupt cause register In-Reply-To: <20240715105156.18388-12-kabel@kernel.org> References: <20240715105156.18388-1-kabel@kernel.org> <20240715105156.18388-12-kabel@kernel.org> Date: Sun, 28 Jul 2024 23:53:53 +0200 Message-ID: <87plqxrxn2.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_145356_249100_0B55BEFD X-CRM114-Status: UNSURE ( 7.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 15 2024 at 12:51, Marek Beh=C3=BAn wrote: > Use MPIC_PER_CPU_IRQS_NR (29) bound instead of BITS_PER_LONG (32) when > iterating the bits of the per-CPU interrupt cause register, since there > are only 29 per-CPU interrupts. The top 3 bits are always zero anyway, > so this may save a couple of cycles in the interrupt handler. I seriously doubt that it saves a single cycle, but adjusting the limit is correct by itself. Thanks, tglx