From: Marc Zyngier <maz@kernel.org>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
Catalin Marinas <catalin.marinas@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v3 02/13] arm64: cpufeatures: Correctly handle signed values
Date: Tue, 09 Jan 2024 11:40:19 +0000 [thread overview]
Message-ID: <87plyau44c.wl-maz@kernel.org> (raw)
In-Reply-To: <86a5pfafbv.wl-maz@kernel.org>
On Mon, 08 Jan 2024 17:46:12 +0000,
Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 11 Dec 2023 12:24:16 +0000,
> Will Deacon <will@kernel.org> wrote:
[...]
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index 646591c67e7a..bc8787f28ffd 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -140,12 +140,42 @@ void dump_cpu_features(void)
> > > pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
> > > }
> > >
> > > +#define __ARM64_MAX_POSITIVE(reg, field) \
> > > + ((reg##_##field##_SIGNED ? \
> > > + BIT(reg##_##field##_WIDTH - 1) : \
> > > + BIT(reg##_##field##_WIDTH)) - 1)
> > > +
> > > +#define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1)
> >
> > I'm struggling to grok these two macros. For example, let's say I have a
> > 4-bit signed field. In that case, the maximum positive value is 7 (0b0111)
> > and the minimum negative value is -8 (0b1000), but the macros above appear
> > to give 0b1000 for both.
>
> Crap. Well spotted. The signed maximum needs to be further adjusted
> like this:
Actually, scratch that. The original code is correct and does return
0b0111 for the max of a signed 4 bit value, and 0b1000 for the min.
The clue is in the bracketing (the '- 1' is applied to the result of
the conditional expression in the max case).
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2024-01-09 11:41 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 11:45 [PATCH v3 00/13] arm64: Add support for FEAT_E2H0, or lack thereof Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 01/13] arm64: Add macro to compose a sysreg field value Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 02/13] arm64: cpufeatures: Correctly handle signed values Marc Zyngier
2023-12-11 12:24 ` Will Deacon
2024-01-08 17:46 ` Marc Zyngier
2024-01-09 11:40 ` Marc Zyngier [this message]
2024-01-30 11:34 ` Will Deacon
2023-11-27 11:45 ` [PATCH v3 03/13] arm64: cpufeature: Correctly display signed override values Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 04/13] arm64: sysreg: Add layout for ID_AA64MMFR4_EL1 Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 05/13] arm64: cpufeature: Add ID_AA64MMFR4_EL1 handling Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 06/13] arm64: cpufeature: Detect E2H0 not being implemented Marc Zyngier
2023-12-11 12:42 ` Will Deacon
2024-01-09 15:16 ` Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 07/13] arm64: cpufeature: Detect HCR_EL2.NV1 being RES0 Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 08/13] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 09/13] arm64: Add override for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 10/13] arm64: Add MIDR-based override infrastructure Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 11/13] arm64: Add MIDR-based overrides for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 12/13] KVM: arm64: Expose ID_AA64MMFR4_EL1 to guests Marc Zyngier
2023-11-27 11:45 ` [PATCH v3 13/13] KVM: arm64: Force guest's HCR_EL2.E2H RES1 when NV1 is not implemented Marc Zyngier
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