From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40A70C77B60 for ; Wed, 26 Apr 2023 21:30:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rakjmMJzx/dUH2V/xixNUwH41vKMSPL0t7LYOHBC+y0=; b=QD7YiJLPfsKInQ NIuzZURwDJmMiRyK0SiyStSF4jjLgUuKTAZbMJXzIMwTmMw1fpIhB2ScMfRpfOogFs20f1c/Kxn2d Atmi0dS5Pou1SReH18RH14Fw8nkw2MjBC8NJ3shtMjthYMgcw7fSejLiSVuHwc4pm5VSfjjMJLO5w ISyGDRLQM8oIxQYB+sS5W/KENaj1mjhkMyP3eJYSJ9lE0FSx9/HVjJXsUHZSdFv3Frn4EVytFrYdX EqolBpJ5nu1cbNe6HlzKoodSvqtIIPx5E9Y283lNC2PgkOF9FUii8La5KwcsksSTWoMnRRAe/2768 ESIPCMnoLM7q1Zfo9Q5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1prmi2-004u2Y-3C; Wed, 26 Apr 2023 21:29:54 +0000 Received: from galois.linutronix.de ([193.142.43.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1prmi0-004u0I-1u for linux-arm-kernel@lists.infradead.org; Wed, 26 Apr 2023 21:29:53 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1682544586; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=fwiQaWIRHQyq7je3uiXIYH4HOfAwQIaSflkAEcF6eh8=; b=B9QDZ0qRvllVXbYmnanLl1ovYM3aOLpWhAF+F82mr/sHwScw4NB2YzXdlUBccBYRxOd9U4 bvKiCt1ex+1KKGOFNXNBHRCU1RmAio5V++JhFLqath6WUBx9PKjA6sFtMPGfzw2SKGuO9F ssit9S+1Bx9s0QR5XCyOyQDfQghfryUJrJPQe+D5efffpWcLyDrmo11g7jPIfN3FCiRicH xKo1OX6bz7cqONbVIeixBvZreanatItV0kQxDGkLA1TtjoaWsQ9nZfsyEhlMLevoNc78YS Q0KC6EUH4hCDdJfvDQr/jj61AOQtCllRSbeqE8GGT+SLNm6wfvRQgPFONTrNbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1682544586; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=fwiQaWIRHQyq7je3uiXIYH4HOfAwQIaSflkAEcF6eh8=; b=WJX2ivJ5pOIVjXh0XT2pQWl0AO1BXk5NMBCI+1TkxCZps2pFiYmBvL8jn/HqSVE36smstx BrCQwH0F6YLGPTAw== To: "Bouska, Zdenek" , Will Deacon , Catalin Marinas Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "Kiszka, Jan" , "linux-rt-users@vger.kernel.org" , Nishanth Menon , Puranjay Mohan Subject: Re: Unfair qspinlocks on ARM64 without LSE atomics => 3ms delay in interrupt handling In-Reply-To: References: Date: Wed, 26 Apr 2023 23:29:45 +0200 Message-ID: <87pm7qxrg6.ffs@tglx> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230426_142952_786226_3A4EDF6E X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 26 2023 at 12:03, Zdenek Bouska wrote: > following patch is my current approach for fixing this issue. I introduced > big_cpu_relax(), which uses Will's implementation [1] on ARM64 without > LSE atomics and original cpu_relax() on any other CPU. Why is this interrupt handling specific? Just because it's the place where you observed it? That's a general issue for any code which uses atomics for forward progress. LL/SC simply does not guarantee that. So if that helps, then this needs to be addressed globaly and not with some crude hack in the interrupt handling code. > Anyone has a better idea how to solve this issue properly? Use hardware with LSE atomics :) Thanks, tglx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel