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Thu, 08 Apr 2021 17:20:18 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lUYGF-008kjK-RV for linux-arm-kernel@lists.infradead.org; Thu, 08 Apr 2021 17:16:23 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 12FE46023B; Thu, 8 Apr 2021 17:16:06 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lUYGC-006Mjo-2Z; Thu, 08 Apr 2021 18:16:04 +0100 Date: Thu, 08 Apr 2021 18:16:03 +0100 Message-ID: <87pmz4ofxo.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/4] arm64: Document values for system registers on boot In-Reply-To: <20210401180942.35815-5-broonie@kernel.org> References: <20210401180942.35815-1-broonie@kernel.org> <20210401180942.35815-5-broonie@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210408_181608_558753_66DA4033 X-CRM114-Status: GOOD ( 30.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mark, On Thu, 01 Apr 2021 19:09:42 +0100, Mark Brown wrote: > > When booting require that the system registers available at or below the > exception level the kernel is entered be initialised but do not specify > what values should be used in the general case, creating some potential > for issues if the kernel does not subsequently configure those registers > explicitly (for example if they are not yet used by the kernel) or where > their effects may create issues during early configuration. > > Specify that where the architecture provides a reset value that value > must be used. > > Signed-off-by: Mark Brown > --- > Documentation/arm64/booting.rst | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst > index 4fcc00add117..d49f568eb79d 100644 > --- a/Documentation/arm64/booting.rst > +++ b/Documentation/arm64/booting.rst > @@ -205,7 +205,9 @@ Before jumping into the kernel, the following conditions must be met: > All writable architected system registers at or below the exception > level where the kernel image will be entered must be initialised by > software at a higher exception level to prevent execution in an UNKNOWN > - state. > + state. Where these architected system registers have reset values > + specified by the architecture they must be initialised to those values > + unless specified more specifically. > > - SCR_EL3.FIQ must have the same value across all CPUs the kernel is > executing on. > -- > 2.20.1 > > Is that always enforceable? Is that even desirable? Take for example ICC_SRE_EL2.SRE. The reset value for that bit is 0. But it is extremely likely that the FW has set this bit to 1 in order to be able to use interrupts with the sysreg interface. However, as outlined in the GIC spec: If software changes this bit from 1 to 0, the results are UNPREDICTABLE. We could go and specify this one, but I fear there is a lot of things we'd have to make explicit... Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel