From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1479C77B7F for ; Tue, 16 May 2023 06:37:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Hsw4hgp/jxGteOiTUzFdNttFbWLZnPkQ4hU/FUPOi9E=; b=WMnvr/Kzl5gt6E chWSLwIkeOyw2PX8Dd9611u4EWr40h7/MIcvE8TQ6IRIt4UeB+jBQrIi74JGbnaLvFPOx0jSl5jY3 EZ7Gwt2qI4QFcEv2CXJeQDFKyebTvPhvt1WkWTd+48GIocGeMueXFcicfz/Vj3VcSFvrRgxutQJ9T aLBeM4Jq4jvwqIRYmg78WHU7OLROB5/3Cb7hO3tNTX2Wby9uqACRe5JxdfqIlxHssrs7DucKh4sjY lTxoMN4le0F0k4Gon4FSV7lABNlTNnj7RBYeQn+fpkdiF8F5I4ooPJgLZnxoc/Qmn3G6iDGgBOhUx U3AJFBs8k7WfoLaf4mzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pyoJK-004X1L-2F; Tue, 16 May 2023 06:37:26 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pyoJH-004WzM-1U for linux-arm-kernel@lists.infradead.org; Tue, 16 May 2023 06:37:24 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1684219039; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=KmQgg157U5ZiEWaWvOuJFjaGuzOX9D+fHsfowoTsDj8=; b=QPI34lfuLTM7cfLvolcJESp5sZKtf336N2yUfdWQlYC1tQnBjG72a4efdkKS0Ebz0vI34G HGvedWOoWK0dOuDI+k9DZkY+pIZ9HU31WA8tLd8bc2ISVhs7A/0D/+VAdpaetge22Uff7K n9XRjBMH41/s63ntdFuxtkz7b7azoOvX0yud+Mwm0OJZFKfk/70IKLGfP6Mv5FK3YADeZZ LrbA22Y4V1Z6roS5IVAmF7UVOBX4kQS7Vdk4rRLd5iQuhxuhwaTla8hZ27OghHiHhXO5w5 GLriB4vELCWXigx03JLL9wVGTaLeF56FKFX4IuZo/hhqNowB8hzomZjAdpNEHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1684219039; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=KmQgg157U5ZiEWaWvOuJFjaGuzOX9D+fHsfowoTsDj8=; b=vHeBuibDTwpl4wMXML5ug2b9+24JDTzT4+wLQO47dw3BdoiZEhpE3oiYwzWDuATmq3ShL5 mD5Ld+ji0kJHlwDA== To: "Russell King (Oracle)" Cc: Andrew Morton , linux-mm@kvack.org, Christoph Hellwig , Uladzislau Rezki , Lorenzo Stoakes , Peter Zijlstra , Baoquan He , John Ogness , linux-arm-kernel@lists.infradead.org, Mark Rutland , Marc Zyngier , x86@kernel.org Subject: Re: Excessive TLB flush ranges In-Reply-To: References: <87a5y5a6kj.ffs@tglx> <87353x9y3l.ffs@tglx> <87zg658fla.ffs@tglx> Date: Tue, 16 May 2023 08:37:18 +0200 Message-ID: <87r0rg93z5.ffs@tglx> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230515_233723_639422_A1B92F81 X-CRM114-Status: GOOD ( 20.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 15 2023 at 22:31, Russell King wrote: > On Mon, May 15, 2023 at 11:11:45PM +0200, Thomas Gleixner wrote: >> But that's not necessarily true for ARM32 as there are no IPIs involved >> on the machine we are using, which is a dual-core Cortex-A9. >> >> So I came up with the hack below, which is equally fast as the full >> flush variant while the performance impact on the other CPUs is minimally >> lower according to perf. >> >> That probably should have another argument which tells how many TLBs >> this flush affects, i.e. 3 in this example, so an architecture can >> sensibly decide whether it wants to use flush all or not. >> @@ -1747,7 +1748,12 @@ static bool __purge_vmap_area_lazy(unsig >> list_last_entry(&local_purge_list, >> struct vmap_area, list)->va_end); >> >> - flush_tlb_kernel_range(start, end); >> + if (tmp.va_end > tmp.va_start) >> + list_add(&tmp.list, &local_purge_list); >> + flush_tlb_kernel_vas(&local_purge_list); >> + if (tmp.va_end > tmp.va_start) >> + list_del(&tmp.list); > > So basically we end up iterating over each VA range, which seems > sensible if the range is large and we have to iterate over it page > by page. Right. > In the case you have, are "start" and "end" set on function entry > to a range, or are they set to ULONG_MAX,0 ? What I'm wondering is > whether we could get away with just having flush_tlb_kernel_vas(). > > Whether that's acceptable to others is a different question :) As I said flush_tlb_kernel_vas() should be void flush_tlb_kernel_vas(struct list_head *list, unsigned int num_entries): So that an architecture can decide whether it's worth to do walk the entries or whether it resorts to a flush all. >> +static void do_flush_vas(void *arg) >> +{ >> + struct list_head *list = arg; >> + struct vmap_area *va; >> + unsigned long addr; >> + >> + list_for_each_entry(va, list, list) { >> + /* flush range by one by one 'invlpg' */ >> + for (addr = va->va_start; addr < va->va_end; addr += PAGE_SIZE) >> + flush_tlb_one_kernel(addr); > > Isn't this just the same as: > flush_tlb_kernel_range(va->va_start, va->va_end); Indeed. Thanks, tglx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel