From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BACDC36008 for ; Sat, 29 Mar 2025 08:14:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BNCXttZkFi/2vw4OPxGWgkdGoNb94Ke4+IKLga20ZsU=; b=IW8REd5nWmFMxd12eN7056h9Si YBoWMYmR29rIsNEmzlO1wCVTcT2kqtWo0BpGv8wGcJ5/ZzRIgsfDaPlArb4Y4uYd/TqZEkMkhlUtm HDluczn//mjgP53FVmuw+umoUlktoBZsueCz433j0RPgedQdo6MEo9kQlDVoMUS/Ahlh2IjB4tUaY WM6f8zNMs9ZWPs+yKlScWkkguowfLtAg5Rz2Gk8LQ1bpCWBgFhW+3d/8yLV62B3rC9NGDOhbgbCkz 3EMs4MLQVWwZ0aF4dgLxIbQmSFLoZbNX6y2EJEEAdw2iSplo5bfQRO0fhHZJJPzpxN72JDjfGSi35 hbEZFBpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1tyRKt-0000000Euim-1QBm; Sat, 29 Mar 2025 08:14:35 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1tyRJ9-0000000EuUl-09Vp for linux-arm-kernel@lists.infradead.org; Sat, 29 Mar 2025 08:12:48 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id CDEF45C40B8; Sat, 29 Mar 2025 08:10:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D9C8C4CEE2; Sat, 29 Mar 2025 08:12:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743235965; bh=XuazfIfZCqDpih+40jG7nHo0OUbNVwTOaEOW4d/Jsiw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=sg323B6tLia20VWLJcu/jMlGVGQpGho+W3vrrmiZFp3JFpbcvAbYB+SvNFyZOJWDf TlrFDnTw15xdLwIEMfXcu92TYR68GF3hsg15mHV0HzsqBw/AM3XK0xkhFUlqlloLb/ 04dSWfVdmQH2MmBZgU/joq4AuoA38Rn47EZBOWaT3h9+iWU9uOwel56nQ79im8Rz/f OaKs5HnvdD0yyzr4zIvvxaEh9oHb0sE3FHQ9Nividprw6bGK87wHUOkl71dhDau91S oUZJu8m81UzQ25Mfg81leievKH1qH4hOzgkNkI/cXoNlAMhIfa+buvU61wrYBM9TM6 GDnV0u2yg+YYA== Received: from 91-161-240-24.subs.proxad.net ([91.161.240.24] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tyRJ4-000X6N-CX; Sat, 29 Mar 2025 08:12:42 +0000 Date: Sat, 29 Mar 2025 08:12:38 +0000 Message-ID: <87semwz24p.wl-maz@kernel.org> From: Marc Zyngier To: Yicong Yang Cc: , , , , , , , , , , , , Subject: Re: [PATCH 2/3] arm64/cpufeature: Add cpucap for HCR_EL2.E2H RES1 (!FEAT_E2H0) In-Reply-To: <20250329034409.21354-3-yangyicong@huawei.com> References: <20250329034409.21354-1-yangyicong@huawei.com> <20250329034409.21354-3-yangyicong@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 91.161.240.24 X-SA-Exim-Rcpt-To: yangyicong@huawei.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shameerali.kolothum.thodi@huawei.com, jonathan.cameron@huawei.com, prime.zeng@hisilicon.com, xuwei5@huawei.com, yangyicong@hisilicon.com, linuxarm@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250329_011247_188169_E2AA7B3A X-CRM114-Status: GOOD ( 27.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 29 Mar 2025 03:44:08 +0000, Yicong Yang wrote: > > From: Yicong Yang > > Arm introduced a "new" feature FEAT_E2H0 indicates that HCR_EL2.E2H can > be programmed to the value 0 for legacy hardwares supported VHE. The > feature is indicated by ID_AA64MMFR4_EL1.E2H0 == 0. It is needed to > detect this feature for KVM mode initialization. Instead of bothering > the existed hardwares, introduce a new cpucap HAS_E2H_RES1 to indicate > FEAT_E2H0 is not supported. Make this a ARM64_CPUCAP_SYSTEM_FEATURE > just like VHE. > > Introduce cpu_has_e2h_res1() for checking the feature's support > which can be used in the early boot stage where CPU capabilities > are not initialized. > > Signed-off-by: Yicong Yang > --- > arch/arm64/include/asm/cpufeature.h | 23 +++++++++++++++++++++++ > arch/arm64/kernel/cpufeature.c | 12 ++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 36 insertions(+) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index c4326f1cb917..b35d393da28d 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -889,6 +889,29 @@ static inline bool cpu_has_hw_af(void) > ID_AA64MMFR1_EL1_HAFDBS_SHIFT); > } > > +/* > + * Check whether FEAT_E2H0 is not supported, in which case HCR_EL2.E2H > + * is implemented as RES1. > + */ > +static __always_inline bool cpu_has_e2h_res1(void) > +{ > + u64 mmfr4; > + u32 val; > + > + /* > + * It's also used for checking the kvm mode cfg in early_param() > + * where boot capabilities is not initialized. In such case read > + * mmfr4 directly. This works same after boot stage since > + * ARM64_HAS_E2H_RES1 is a system feature, the cached sanitised > + * value keeps same with every single CPU. > + */ > + mmfr4 = read_sysreg_s(SYS_ID_AA64MMFR4_EL1); This will result in traps to EL2 with nested. Are you expecting this to be used on any form of hot paths? > + val = cpuid_feature_extract_signed_field(mmfr4, > + ID_AA64MMFR4_EL1_E2H0_SHIFT); > + > + return val != ID_AA64MMFR4_EL1_E2H0_IMP; This is going to break badly on Apple HW, which predate the "!FEAT_E2H0" relaxation and yet have HCR_EL2.E2H RAO/WI and ID_AA64MMFR4_EL1.E2H0==0. The curent code was carefully designed to *avoid* doing this, because the kernel doesn't really need to know anything about FEAT_E2H0 apart from the very early boot. What do we gain with this? M. -- Jazz isn't dead. It just smells funny.