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Thu, 27 Jan 2022 18:34:13 +0000 Date: Thu, 27 Jan 2022 18:34:12 +0000 Message-ID: <87sft958pn.wl-maz@kernel.org> From: Marc Zyngier To: James Morse Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Catalin Marinas , Will Deacon , Shuah Khan , Mark Brown Subject: Re: [PATCH 3/3] arm64: insn: Generate 64 bit mask immediates correctly In-Reply-To: <20220127162127.2391947-4-james.morse@arm.com> References: <20220127162127.2391947-1-james.morse@arm.com> <20220127162127.2391947-4-james.morse@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: james.morse@arm.com, linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, shuah@kernel.org, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_103417_000767_23FAF2EB X-CRM114-Status: GOOD ( 30.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 27 Jan 2022 16:21:27 +0000, James Morse wrote: > > When the insn framework is used to encode an AND/ORR/EOR instruction, > aarch64_encode_immediate() is used to pick the immr imms values. > > If the immediate is a 64bit mask, with bit 63 set, and zeros in any > of the upper 32 bits, the immr value is incorrectly calculated meaning > the wrong mask is generated. > For example, 0x8000000000000001 should have an immr of 1, but 32 is used, > meaning the resulting mask is 0x0000000300000000. > > It would appear eBPF is unable to hit these cases, as build_insn()'s > imm value is a s32, so when used with BPF_ALU64, the sign-extended > u64 immediate would always have all-1s or all-0s in the upper 32 bits. > > KVM does not generate a va_mask with any of the top bits set as these > VA wouldn't be usable with TTBR0_EL2. > > This happens because the rotation is calculated from fls(~imm), which > takes an unsigned int, but the immediate may be 64bit. > > Use fls64() so the 64bit mask doesn't get truncated to a u32. > > Signed-off-by: James Morse > --- > arch/arm64/lib/insn.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c > index 8888e407032f..90253af7e294 100644 > --- a/arch/arm64/lib/insn.c > +++ b/arch/arm64/lib/insn.c > @@ -1381,7 +1381,7 @@ static u32 aarch64_encode_immediate(u64 imm, > * Compute the rotation to get a continuous set of > * ones, with the first bit set at position 0 > */ > - ror = fls(~imm); > + ror = fls64(~imm); > } > > /* Oh crap, not again... :-( Clearly, my initial test harness wasn't as good as I thought. Out for morbid curiosity, how was this found? Brown-paper-bag-for: Marc Zyngier Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel