From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1314EC433ED for ; Thu, 1 Apr 2021 15:16:08 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78EE261367 for ; Thu, 1 Apr 2021 15:16:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78EE261367 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Subject:Cc:To: From:Message-ID:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Fs7xeuXuBirj/zV09o4YXisD543KCI/St13I4h2XK6U=; b=T22b8cI8IaqsK7bdTw+zzxctE rB1W8b/CJGY2UfP0nFfTUqcqfVuG+Owa6HJv2x7K65CCjF+/lBhuahicZ2VB1SqXUCo82BvIemLuO 94VXwGHzFwz3Qn+EJpsIJXt3C0GsZ19Xjbju0evcgRIFqzZZeEzwC+WgRPiwpwPCZ3OrTgdS5j/X2 dRmHkCEWNdbi1Q7sByhtBX1t1dkbYzyvJDI8DXE/WBDLQ6fG8S7wbqV+0ducGEhyiXKZ/j0Tbb+vH fVFYv6txD5cSKu9+YOBdXnAQQdwAXgXECQrSuJnu+XSWbDnHpZWhzuFPeo7RW9sHeWBDEBSGmlB7H MTTQCMHCg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRz1y-009y8M-UZ; Thu, 01 Apr 2021 15:14:47 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRz1u-009y6v-3T for linux-arm-kernel@lists.infradead.org; Thu, 01 Apr 2021 15:14:44 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B04C861367; Thu, 1 Apr 2021 15:14:38 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lRz1o-0057Fj-JL; Thu, 01 Apr 2021 16:14:36 +0100 Date: Thu, 01 Apr 2021 16:14:35 +0100 Message-ID: <87sg4aox44.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: Disable fine grained traps on boot In-Reply-To: <20210401124936.56877-1-broonie@kernel.org> References: <20210401124936.56877-1-broonie@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_161442_540330_088584B6 X-CRM114-Status: GOOD ( 21.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Thanks Will for the bounce. On Thu, 01 Apr 2021 13:49:36 +0100, Mark Brown wrote: > > The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses > to small sets of registers and instructions from EL1 and EL0. Currently > Linux makes no use of this feature, ensure that it is not active at boot by > disabling the traps during EL2 setup. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/el2_setup.h | 21 +++++++++++++++++++++ > arch/arm64/include/asm/sysreg.h | 6 ++++++ > 2 files changed, 27 insertions(+) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index d77d358f9395..f94ef3a76877 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -131,6 +131,26 @@ > .Lskip_sve_\@: > .endm > > +/* Disable any fine grained traps */ > +.macro __init_el2_fgt > + mrs x1, id_aa64mmfr0_el1 > + ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4 > + cbz x1, .Lskip_fgt_\@ > + > + msr_s SYS_HDFGRTR_EL2, xzr > + msr_s SYS_HDFGWTR_EL2, xzr > + msr_s SYS_HFGRTR_EL2, xzr > + msr_s SYS_HFGITR_EL2, xzr > + msr_s SYS_HFGWTR_EL2, xzr nit: consider grouping SYS_HFGWTR_EL2 and SYS_HFGRTR_EL2 together, since they affect the same registers. > + > + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU > + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4 > + cbz x1, .Lskip_fgt_\@ > + > + msr_s SYS_HAFGRTR_EL2, xzr Do we need to document the need for SCR_EL3.FGTEn to be set so that these register accesses don't trap? That'd be consistent with what we do for other features (PtrAuth, AMU...). > +.Lskip_fgt_\@: > +.endm > + > .macro __init_el2_nvhe_prepare_eret > mov x0, #INIT_PSTATE_EL1 > msr spsr_el2, x0 > @@ -155,6 +175,7 @@ > __init_el2_nvhe_idregs > __init_el2_nvhe_cptr > __init_el2_nvhe_sve > + __init_el2_fgt > __init_el2_nvhe_prepare_eret > .endm > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index d4a5fca984c3..b35468927363 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -475,9 +475,15 @@ > #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) > > #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) > +#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) > +#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) > +#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) > #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) > #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) > +#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) > +#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) > +#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel