* [PATCH] arm64: Disable fine grained traps on boot
@ 2021-04-01 12:49 Mark Brown
2021-04-01 15:14 ` Marc Zyngier
0 siblings, 1 reply; 4+ messages in thread
From: Mark Brown @ 2021-04-01 12:49 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses
to small sets of registers and instructions from EL1 and EL0. Currently
Linux makes no use of this feature, ensure that it is not active at boot by
disabling the traps during EL2 setup.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/el2_setup.h | 21 +++++++++++++++++++++
arch/arm64/include/asm/sysreg.h | 6 ++++++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index d77d358f9395..f94ef3a76877 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -131,6 +131,26 @@
.Lskip_sve_\@:
.endm
+/* Disable any fine grained traps */
+.macro __init_el2_fgt
+ mrs x1, id_aa64mmfr0_el1
+ ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
+ cbz x1, .Lskip_fgt_\@
+
+ msr_s SYS_HDFGRTR_EL2, xzr
+ msr_s SYS_HDFGWTR_EL2, xzr
+ msr_s SYS_HFGRTR_EL2, xzr
+ msr_s SYS_HFGITR_EL2, xzr
+ msr_s SYS_HFGWTR_EL2, xzr
+
+ mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
+ ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
+ cbz x1, .Lskip_fgt_\@
+
+ msr_s SYS_HAFGRTR_EL2, xzr
+.Lskip_fgt_\@:
+.endm
+
.macro __init_el2_nvhe_prepare_eret
mov x0, #INIT_PSTATE_EL1
msr spsr_el2, x0
@@ -155,6 +175,7 @@
__init_el2_nvhe_idregs
__init_el2_nvhe_cptr
__init_el2_nvhe_sve
+ __init_el2_fgt
__init_el2_nvhe_prepare_eret
.endm
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d4a5fca984c3..b35468927363 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -475,9 +475,15 @@
#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
+#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
+#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
+#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
+#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
+#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
+#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
--
2.20.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: Disable fine grained traps on boot
2021-04-01 12:49 [PATCH] arm64: Disable fine grained traps on boot Mark Brown
@ 2021-04-01 15:14 ` Marc Zyngier
2021-04-01 15:48 ` Mark Brown
0 siblings, 1 reply; 4+ messages in thread
From: Marc Zyngier @ 2021-04-01 15:14 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Mark Rutland, linux-arm-kernel
Thanks Will for the bounce.
On Thu, 01 Apr 2021 13:49:36 +0100,
Mark Brown <broonie@kernel.org> wrote:
>
> The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses
> to small sets of registers and instructions from EL1 and EL0. Currently
> Linux makes no use of this feature, ensure that it is not active at boot by
> disabling the traps during EL2 setup.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/el2_setup.h | 21 +++++++++++++++++++++
> arch/arm64/include/asm/sysreg.h | 6 ++++++
> 2 files changed, 27 insertions(+)
>
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index d77d358f9395..f94ef3a76877 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -131,6 +131,26 @@
> .Lskip_sve_\@:
> .endm
>
> +/* Disable any fine grained traps */
> +.macro __init_el2_fgt
> + mrs x1, id_aa64mmfr0_el1
> + ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
> + cbz x1, .Lskip_fgt_\@
> +
> + msr_s SYS_HDFGRTR_EL2, xzr
> + msr_s SYS_HDFGWTR_EL2, xzr
> + msr_s SYS_HFGRTR_EL2, xzr
> + msr_s SYS_HFGITR_EL2, xzr
> + msr_s SYS_HFGWTR_EL2, xzr
nit: consider grouping SYS_HFGWTR_EL2 and SYS_HFGRTR_EL2 together,
since they affect the same registers.
> +
> + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
> + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
> + cbz x1, .Lskip_fgt_\@
> +
> + msr_s SYS_HAFGRTR_EL2, xzr
Do we need to document the need for SCR_EL3.FGTEn to be set so that
these register accesses don't trap? That'd be consistent with what we
do for other features (PtrAuth, AMU...).
> +.Lskip_fgt_\@:
> +.endm
> +
> .macro __init_el2_nvhe_prepare_eret
> mov x0, #INIT_PSTATE_EL1
> msr spsr_el2, x0
> @@ -155,6 +175,7 @@
> __init_el2_nvhe_idregs
> __init_el2_nvhe_cptr
> __init_el2_nvhe_sve
> + __init_el2_fgt
> __init_el2_nvhe_prepare_eret
> .endm
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index d4a5fca984c3..b35468927363 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -475,9 +475,15 @@
> #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
>
> #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
> +#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
> +#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
> +#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
> #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
> #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
> +#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
> +#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
> +#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
> #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
> #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
> #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: Disable fine grained traps on boot
2021-04-01 15:14 ` Marc Zyngier
@ 2021-04-01 15:48 ` Mark Brown
2021-04-01 17:03 ` Marc Zyngier
0 siblings, 1 reply; 4+ messages in thread
From: Mark Brown @ 2021-04-01 15:48 UTC (permalink / raw)
To: Marc Zyngier; +Cc: Catalin Marinas, Will Deacon, Mark Rutland, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1129 bytes --]
On Thu, Apr 01, 2021 at 04:14:35PM +0100, Marc Zyngier wrote:
> On Thu, 01 Apr 2021 13:49:36 +0100,
> Mark Brown <broonie@kernel.org> wrote:
> > + msr_s SYS_HFGRTR_EL2, xzr
> > + msr_s SYS_HFGITR_EL2, xzr
> > + msr_s SYS_HFGWTR_EL2, xzr
> nit: consider grouping SYS_HFGWTR_EL2 and SYS_HFGRTR_EL2 together,
> since they affect the same registers.
Ack, I'd sorted them numerically IIRC.
> > + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
> > + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
> > + cbz x1, .Lskip_fgt_\@
> > + msr_s SYS_HAFGRTR_EL2, xzr
> Do we need to document the need for SCR_EL3.FGTEn to be set so that
> these register accesses don't trap? That'd be consistent with what we
> do for other features (PtrAuth, AMU...).
Yes, good point. We should if this is going in - this is the result of
some other stuff I've been sending to document disabling these on boot,
Will wanted to have code doing that, so I'll pull that into there. It
does end up being a bit weird that we demand this be enabled so we can
explicitly not use it, but better to do that so we can in future decide
to take advantage of it.
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: Disable fine grained traps on boot
2021-04-01 15:48 ` Mark Brown
@ 2021-04-01 17:03 ` Marc Zyngier
0 siblings, 0 replies; 4+ messages in thread
From: Marc Zyngier @ 2021-04-01 17:03 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Mark Rutland, linux-arm-kernel
On Thu, 01 Apr 2021 16:48:05 +0100,
Mark Brown <broonie@kernel.org> wrote:
>
> On Thu, Apr 01, 2021 at 04:14:35PM +0100, Marc Zyngier wrote:
> > On Thu, 01 Apr 2021 13:49:36 +0100,
> > Mark Brown <broonie@kernel.org> wrote:
>
> > > + msr_s SYS_HFGRTR_EL2, xzr
> > > + msr_s SYS_HFGITR_EL2, xzr
> > > + msr_s SYS_HFGWTR_EL2, xzr
>
> > nit: consider grouping SYS_HFGWTR_EL2 and SYS_HFGRTR_EL2 together,
> > since they affect the same registers.
>
> Ack, I'd sorted them numerically IIRC.
>
> > > + mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
> > > + ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
> > > + cbz x1, .Lskip_fgt_\@
>
> > > + msr_s SYS_HAFGRTR_EL2, xzr
>
> > Do we need to document the need for SCR_EL3.FGTEn to be set so that
> > these register accesses don't trap? That'd be consistent with what we
> > do for other features (PtrAuth, AMU...).
>
> Yes, good point. We should if this is going in - this is the result of
> some other stuff I've been sending to document disabling these on boot,
> Will wanted to have code doing that, so I'll pull that into there. It
> does end up being a bit weird that we demand this be enabled so we can
> explicitly not use it, but better to do that so we can in future decide
> to take advantage of it.
I definitely have plans for this feature right now, as some of the
traps that KVM uses could be minimised using FGT, so I don't believe
the feature will stay unused for too long.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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2021-04-01 12:49 [PATCH] arm64: Disable fine grained traps on boot Mark Brown
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