[PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Fang Xiang]

In non-coherent GIC design, ITS tables should be clean and flushed
to the PoV of the ITS before writing GITS_BASER<n> registers. And
hoist the quirked non-shareable attributes earlier to save effort
in tables setup.

Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>

Link to v1:
https://lore.kernel.org/all/20231026020116.4238-1-fangxiang3@xiaomi.com/

v1 -> v2:
    - Flush ITS tables before writing GITS_BASER<n> registers
    - Hoist the quirked non-shareable attributes earlier
---
 drivers/irqchip/irq-gic-v3-its.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 75a2dd550625..d76d44ea2de1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2379,12 +2379,12 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
 		break;
 	}
 
+	if (!shr)
+		gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+
 	its_write_baser(its, baser, val);
 	tmp = baser->val;
 
-	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
-		tmp &= ~GITS_BASER_SHAREABILITY_MASK;
-
 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 		/*
 		 * Shareability didn't stick. Just use
@@ -2394,10 +2394,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
 		 * non-cacheable as well.
 		 */
 		shr = tmp & GITS_BASER_SHAREABILITY_MASK;
-		if (!shr) {
+		if (!shr)
 			cache = GITS_BASER_nC;
-			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
-		}
+
 		goto retry_baser;
 	}
 
@@ -2609,6 +2608,11 @@ static int its_alloc_tables(struct its_node *its)
 		/* erratum 24313: ignore memory access type */
 		cache = GITS_BASER_nCnB;
 
+	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {
+		cache = GITS_BASER_nC;
+		shr = 0;
+	}
+
 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 		struct its_baser *baser = its->tables + i;
 		u64 val = its_read_baser(its, baser);
-- 
2.34.1


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Re: [PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Thomas Gleixner]

On Fri, Oct 27 2023 at 11:10, Fang Xiang wrote:
> In non-coherent GIC design, ITS tables should be clean and flushed
> to the PoV of the ITS before writing GITS_BASER<n> registers. And
> hoist the quirked non-shareable attributes earlier to save effort
> in tables setup.
>
> Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>

Seriously? You claim authorship for a patch which was written by Marc:

   https://lore.kernel.org/all/87sf5x6cdu.wl-maz@kernel.org

without even the courtesy of giving him credit via 'Originally-by' ?

That's not how it works.

Thanks,

        tglx

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Re: [PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.

[Fang Xiang]

On Fri, Oct 27, 2023 at 10:16:57AM +0200, Thomas Gleixner wrote:
> On Fri, Oct 27 2023 at 11:10, Fang Xiang wrote:
> > In non-coherent GIC design, ITS tables should be clean and flushed
> > to the PoV of the ITS before writing GITS_BASER<n> registers. And
> > hoist the quirked non-shareable attributes earlier to save effort
> > in tables setup.
> >
> > Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> 
> Seriously? You claim authorship for a patch which was written by Marc:
> 
>    https://lore.kernel.org/all/87sf5x6cdu.wl-maz@kernel.org
> 
> without even the courtesy of giving him credit via 'Originally-by' ?
> 
> That's not how it works.
> 
> Thanks,
> 
>         tglx

I am sorry. That's a terrible mistake. Just want to fix this issue as
soon as possible and I am learning how to contribute to the community 
in a right way.

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