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Thu, 25 Feb 2021 18:30:11 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lFLOp-0001MA-H3 for linux-arm-kernel@lists.infradead.org; Thu, 25 Feb 2021 18:30:08 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3091E64F03; Thu, 25 Feb 2021 18:30:06 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lFLOm-00FuZb-5g; Thu, 25 Feb 2021 18:30:04 +0000 Date: Thu, 25 Feb 2021 18:30:03 +0000 Message-ID: <87wnuwyp90.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [RFC PATCH 1/4] KVM: arm64: Move the clean of dcache to the map handler In-Reply-To: <43f05bfa-6b8b-a7d3-4355-0f1486aa6634@arm.com> References: <20210208112250.163568-1-wangyanan55@huawei.com> <20210208112250.163568-2-wangyanan55@huawei.com> <871rd41ngf.wl-maz@kernel.org> <43f05bfa-6b8b-a7d3-4355-0f1486aa6634@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, wangyanan55@huawei.com, kvm@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, will@kernel.org, kvmarm@lists.cs.columbia.edu X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210225_133007_753823_6E7C62ED X-CRM114-Status: GOOD ( 41.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Yanan Wang , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 25 Feb 2021 17:39:00 +0000, Alexandru Elisei wrote: > > Hi Marc, > > On 2/25/21 9:55 AM, Marc Zyngier wrote: > > Hi Yanan, > > > > On Mon, 08 Feb 2021 11:22:47 +0000, > > Yanan Wang wrote: > >> We currently uniformly clean dcache in user_mem_abort() before calling the > >> fault handlers, if we take a translation fault and the pfn is cacheable. > >> But if there are concurrent translation faults on the same page or block, > >> clean of dcache for the first time is necessary while the others are not. > >> > >> By moving clean of dcache to the map handler, we can easily identify the > >> conditions where CMOs are really needed and avoid the unnecessary ones. > >> As it's a time consuming process to perform CMOs especially when flushing > >> a block range, so this solution reduces much load of kvm and improve the > >> efficiency of creating mappings. > > That's an interesting approach. However, wouldn't it be better to > > identify early that there is already something mapped, and return to > > the guest ASAP? > > Wouldn't that introduce overhead for the common case, when there's > only one VCPU that faults on an address? For each data abort caused > by a missing stage 2 entry we would now have to determine if the IPA > isn't already mapped and that means walking the stage 2 tables. The problem is that there is no easy to define "common case". It all depends on what you are running in the guest. > Or am I mistaken and either: > > (a) The common case is multiple simultaneous translation faults from > different VCPUs on the same IPA. Or > > (b) There's a fast way to check if an IPA is mapped at stage 2 and > the overhead would be negligible. Checking that something is mapped is simple enough: walk the S2 PT (in SW or using AT/PAR), and return early if there is *anything*. You already have taken the fault, which is the most expensive part of the handling. > > > > > Can you quantify the benefit of this patch alone? And this ^^^ part is crucial to evaluating the merit of this patch, specially outside of the micro-benchmark space. > > > >> Signed-off-by: Yanan Wang > >> --- > >> arch/arm64/include/asm/kvm_mmu.h | 16 -------------- > >> arch/arm64/kvm/hyp/pgtable.c | 38 ++++++++++++++++++++------------ > >> arch/arm64/kvm/mmu.c | 14 +++--------- > >> 3 files changed, 27 insertions(+), 41 deletions(-) > >> > >> diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > >> index e52d82aeadca..4ec9879e82ed 100644 > >> --- a/arch/arm64/include/asm/kvm_mmu.h > >> +++ b/arch/arm64/include/asm/kvm_mmu.h > >> @@ -204,22 +204,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > >> return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > >> } > >> > >> -static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) > >> -{ > >> - void *va = page_address(pfn_to_page(pfn)); > >> - > >> - /* > >> - * With FWB, we ensure that the guest always accesses memory using > >> - * cacheable attributes, and we don't have to clean to PoC when > >> - * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > >> - * PoU is not required either in this case. > >> - */ > >> - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > >> - return; > >> - > >> - kvm_flush_dcache_to_poc(va, size); > >> -} > >> - > >> static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > >> unsigned long size) > >> { > >> diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > >> index 4d177ce1d536..2f4f87021980 100644 > >> --- a/arch/arm64/kvm/hyp/pgtable.c > >> +++ b/arch/arm64/kvm/hyp/pgtable.c > >> @@ -464,6 +464,26 @@ static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, > >> return 0; > >> } > >> > >> +static bool stage2_pte_cacheable(kvm_pte_t pte) > >> +{ > >> + u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > >> + return memattr == PAGE_S2_MEMATTR(NORMAL); > >> +} > >> + > >> +static void stage2_flush_dcache(void *addr, u64 size) > >> +{ > >> + /* > >> + * With FWB, we ensure that the guest always accesses memory using > >> + * cacheable attributes, and we don't have to clean to PoC when > >> + * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > >> + * PoU is not required either in this case. > >> + */ > >> + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > >> + return; > >> + > >> + __flush_dcache_area(addr, size); > >> +} > >> + > >> static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > >> kvm_pte_t *ptep, > >> struct stage2_map_data *data) > >> @@ -495,6 +515,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > >> put_page(page); > >> } > >> > >> + /* Flush data cache before installation of the new PTE */ > >> + if (stage2_pte_cacheable(new)) > >> + stage2_flush_dcache(__va(phys), granule); > >> + > >> smp_store_release(ptep, new); > >> get_page(page); > >> data->phys += granule; > >> @@ -651,20 +675,6 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, > >> return ret; > >> } > >> > >> -static void stage2_flush_dcache(void *addr, u64 size) > >> -{ > >> - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > >> - return; > >> - > >> - __flush_dcache_area(addr, size); > >> -} > >> - > >> -static bool stage2_pte_cacheable(kvm_pte_t pte) > >> -{ > >> - u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > >> - return memattr == PAGE_S2_MEMATTR(NORMAL); > >> -} > >> - > >> static int stage2_unmap_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, > >> enum kvm_pgtable_walk_flags flag, > >> void * const arg) > >> diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c > >> index 77cb2d28f2a4..d151927a7d62 100644 > >> --- a/arch/arm64/kvm/mmu.c > >> +++ b/arch/arm64/kvm/mmu.c > >> @@ -609,11 +609,6 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, > >> kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); > >> } > >> > >> -static void clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) > >> -{ > >> - __clean_dcache_guest_page(pfn, size); > >> -} > >> - > >> static void invalidate_icache_guest_page(kvm_pfn_t pfn, unsigned long size) > >> { > >> __invalidate_icache_guest_page(pfn, size); > >> @@ -882,9 +877,6 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, > >> if (writable) > >> prot |= KVM_PGTABLE_PROT_W; > >> > >> - if (fault_status != FSC_PERM && !device) > >> - clean_dcache_guest_page(pfn, vma_pagesize); > >> - > >> if (exec_fault) { > >> prot |= KVM_PGTABLE_PROT_X; > >> invalidate_icache_guest_page(pfn, vma_pagesize); > > It seems that the I-side CMO now happens *before* the D-side, which > > seems odd. What prevents the CPU from speculatively fetching > > instructions in the interval? I would also feel much more confident if > > the two were kept close together. > > I noticed yet another thing which I don't understand. When the CPU > has the ARM64_HAS_CACHE_DIC featue (CTR_EL0.DIC = 1), which means > instruction invalidation is not required for data to instruction > coherence, we still do the icache invalidation. I am wondering if > the invalidation is necessary in this case. It isn't, and DIC is already taken care of in the leaf functions (see __flush_icache_all() and invalidate_icache_range()). > If it's not, then I think it's correct (and straightforward) to move > the icache invalidation to stage2_map_walker_try_leaf() after the > dcache clean+inval and make it depend on the new mapping being > executable *and* !cpus_have_const_cap(ARM64_HAS_CACHE_DIC). It would also need to be duplicated on the permission fault path. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel