Re: [PATCH v19 04/14] KVM: arm64: Ensure GCS memory effects are visible

[Marc Zyngier <maz@kernel.org>]

On Wed, 19 Aug 2026 19:08:01 +0100,
Mark Brown <broonie@kernel.org> wrote:
> 
> On Wed, Aug 19, 2026 at 06:23:11PM +0100, Leonardo Bras wrote:
> 
> > You state that we do _not_ use GCS in the hypervisor, nor in the host.
> > I understand that we GCSB() when we exit the vcpu context, but why would we 
> > need to GCSB() before getting back in?
> 
> > If cpus will GCSB() on guest_exit, and host/hyp does not use GCS, there 
> > should be no GCS pending operation at the entry point.
> 
> That's there to ensure that updates written by another PE are seen,
> following the same pattern as DDI0487 M.c K10.6.5 example K10-8 (or the
> prior migration between PEs example, that has barriers due to the stack
> switch operations rather than as distinct instructions).

This makes no sense at all. The guest itself is in charge of its own
coherency.

From the PoV of the hypervisor, this only needs to be guaranteed when
a vcpu is migrated from one physical CPU to another, as this is
invisible to the guest.

Given that this can only happen on in the interval between vcpu_put()
and vcpu_load(), the sole location where this could make any sense is
at vcpu_put() time. And even that can be relaxed in the NV case, where
we transition between ELs rather than CPUs.

Hammering things in the run loop is both expensive and pointless.

	M.

-- 
Jazz isn't dead. It just smells funny.