From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Michael Walle" <mwalle@kernel.org>
Cc: "Pratyush Yadav" <pratyush@kernel.org>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
"Richard Weinberger" <richard@nod.at>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Nicolas Ferre" <nicolas.ferre@microchip.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Claudiu Beznea" <claudiu.beznea@tuxon.dev>,
"Steam Lin" <STLin2@winbond.com>,
"Hsin-Yi Wang" <hsinyi@chromium.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
<linux-mtd@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support
Date: Wed, 05 Aug 2026 16:04:52 +0200 [thread overview]
Message-ID: <87y0ekek8r.fsf@bootlin.com> (raw)
In-Reply-To: <87mrv2exwp.fsf@bootlin.com> (Miquel Raynal's message of "Tue, 04 Aug 2026 16:57:26 +0200")
Hello Michael,
>>> +int spi_nor_read_srs(struct spi_nor *nor, u8 *sr1, u8 *sr2)
>>
>> nitpick, i think this is a weird name. But maybe it's just me.
>>
>> What if we'd just make the one status register as u32? I mean in the
>> winbond datasheet it's called S7-S0 and S15-S8. That way we also
>> don't need a two byte qe_mask. To optimize the standard usecase to
>> poll the WIP bit, we could add a byte mask.
I experimented a bit the u32 status register, I don't think it is a good
idea.
My target of improving the readability is completely defeated by the
fact that:
- all the callers need to add extra maths to explain what SR
they want
- endianness shall be handled, people always get it wrong (including
me), so why bother if an array just makes the whole thing simpler?
- 16-bit accesses get more convoluted, we need extra
get_/put_unaligned_le32() calls and pack/unpack bytes in the hot path
- 8-bit accesses imply an extensive use of FIELD_GET(GENMASK(),) macros,
which make the whole fonction totally non obvious anymore.
Whereas, a simple:
if (sr2)
*sr2 = foo;
is self explanatory. I also do not really get the wish for a QE mask
instead of a two bytes array.
So I will rename the "srs" naming that you dislike, I will group the
opcodes in a big structure, change the baseline default to match your
suggestion and follow-up with the other minor comments, but I believe
I'm going to avoid the u32 switch.
Thanks,
Miquèl
next prev parent reply other threads:[~2026-08-05 14:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 16:05 [PATCH 0/5] mtd: spi-nor: Massive QE handling cleanup and Winbond RV chips addition Miquel Raynal
2026-05-29 16:05 ` [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support Miquel Raynal
2026-07-07 9:43 ` Michael Walle
2026-08-04 14:57 ` Miquel Raynal
2026-08-05 14:04 ` Miquel Raynal [this message]
2026-08-06 7:38 ` Miquel Raynal
2026-05-29 16:05 ` [PATCH 2/5] mtd: spi-nor: Add support for the new JESD216 rev F QER field Miquel Raynal
2026-05-29 16:05 ` [PATCH 3/5] mtd: spi-nor: Move the SFDP header structure to a C header Miquel Raynal
2026-05-29 16:05 ` [PATCH 4/5] mtd: spi-nor: winbond: Add support for W25Q02RV-M Miquel Raynal
2026-05-29 16:05 ` [PATCH 5/5] mtd: spi-nor: winbond: Add support for W25Q51RV-M Miquel Raynal
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