From: Marc Zyngier <maz@kernel.org>
To: "Jitindar Singh, Suraj" <surajjs@amazon.com>
Cc: "jingzhangos@google.com" <jingzhangos@google.com>,
"oupton@google.com" <oupton@google.com>,
"alexandru.elisei@arm.com" <alexandru.elisei@arm.com>,
"james.morse@arm.com" <james.morse@arm.com>,
"suzuki.poulose@arm.com" <suzuki.poulose@arm.com>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"rananta@google.com" <rananta@google.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"reijiw@google.com" <reijiw@google.com>,
"will@kernel.org" <will@kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"tabba@google.com" <tabba@google.com>
Subject: Re: [PATCH v8 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3
Date: Sat, 20 May 2023 09:45:01 +0100 [thread overview]
Message-ID: <87y1ljo0he.wl-maz@kernel.org> (raw)
In-Reply-To: <bdba9f6db5bc2f617f2242c3ddbff8adb7c00c91.camel@amazon.com>
On Sat, 20 May 2023 00:04:53 +0100,
"Jitindar Singh, Suraj" <surajjs@amazon.com> wrote:
>
> On Fri, 2023-05-19 at 10:16 +0100, Marc Zyngier wrote:
> > CAUTION: This email originated from outside of the organization. Do
> > not click links or open attachments unless you can confirm the sender
> > and know the content is safe.
> >
> >
> >
> > On Thu, 18 May 2023 22:08:15 +0100,
> > "Jitindar Singh, Suraj" <surajjs@amazon.com> wrote:
> > >
> > > Reading init_cpu_ftr_reg() is hurting my head :p but don't we have
> > > basically 2 cases here?
> > >
> > > 1. We are unaffected by spectre|meltdown i.e.
> > > arm64_get_[spectre|meltdown]_v2_state() will return
> > > SPECTRE_UNAFFECTED
> > > and we will set the limit to 1 for the csv[1|2] bit fields in
> > > read_sanitised_id_aa64pfr0_el1()
> > >
> > > or
> > >
> > > 2. We ARE affected by spectre|meltdown in which case
> > > arm64_get_[spectre|meltdown]_v2_state() will be
> > > SPECTRE_VULNERABLE|SPECTRE_MITIGATED in which case
> > > read_sanitised_ftr_reg() will return a value with csv[1|2] set to 0
> > > essentially setting the limit for either of these bit fields to 0
> > > in
> > > read_sanitised_id_aa64pfr0_el1().
> >
> > What is "WE"?
>
> The CPU
Hilarious.
>
> >
> > >
> > > Are we trying to catch the case where csv[1|2] is 0 on the host but
> > > we
> > > are unaffected as detected by e.g. cpuid and that cpu happens to
> > > incorrectly not set csv[1|2] in the ID register but we still want
> > > to
> > > allow the guest to see those bits as set?
> > >
> > > This isn't really related to the CR as I know this is existing code
> > > which has just been moved around and sorry if I'm missing something
> > > obvious.
> >
> > This code is called from *userspace*, and tries to cope with a VM
> > being restored. So we have 3 (not 2 cases):
> >
> > - both the source and the destination have the same level of CSVx
> > support, and all is great in the world
> >
> > - the source has CSVx==0, while the destination has CSVx=1. All good,
> > as we won't be lying to the guest, and the extra mitigation
> > executed by the guest isn't a functional problem. The guest will
> > still see CSVx=0 after migration.
> >
> > - the source has CSVx=1, while the destination has CSVx=0. This isn't
> > an acceptable situation, and we return an error
> >
> > Is that clearer?
>
> Yes thanks, that all makes sense.
>
> My initial question was why we needed to enforce the limit essentially
> twice in set_id_aa64pfr0_el1().
>
> Once with:
> /*
> * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
> * it doesn't promise more than what is actually provided (the
> * guest could otherwise be covered in ectoplasmic residue).
> */
> csv2 = cpuid_feature_extract_unsigned_field(val,
> ID_AA64PFR0_EL1_CSV2_SHIFT);
> if (csv2 > 1 ||
> (csv2 && arm64_get_spectre_v2_state() !=
> SPECTRE_UNAFFECTED))
> return -EINVAL;
>
> /* Same thing for CSV3 */
> csv3 = cpuid_feature_extract_unsigned_field(val,
> ID_AA64PFR0_EL1_CSV3_SHIFT);
> if (csv3 > 1 ||
> (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
> return -EINVAL;
>
> And then again with the check in arm64_check_features().
Ah, I see what you mean. Yes, this isn't right. I asked for the
generic code to be used in the past, but the old stuff was left
in. Which is obviously not great.
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2023-05-20 8:45 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-03 17:16 [PATCH v8 0/6] Support writable CPU ID registers from userspace Jing Zhang
2023-05-03 17:16 ` [PATCH v8 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file Jing Zhang
2023-05-16 16:11 ` Marc Zyngier
2023-05-16 19:14 ` Jing Zhang
2023-05-03 17:16 ` [PATCH v8 2/6] KVM: arm64: Save ID registers' sanitized value per guest Jing Zhang
2023-05-17 7:41 ` Marc Zyngier
2023-05-17 16:28 ` Jing Zhang
2023-05-03 17:16 ` [PATCH v8 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] Jing Zhang
2023-05-03 23:43 ` kernel test robot
2023-05-03 17:16 ` [PATCH v8 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
2023-05-03 17:16 ` [PATCH v8 5/6] KVM: arm64: Reuse fields of sys_reg_desc for idreg Jing Zhang
2023-05-16 10:26 ` Cornelia Huck
2023-05-16 19:10 ` Jing Zhang
2023-05-03 17:16 ` [PATCH v8 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang
2023-05-17 22:00 ` Jitindar Singh, Suraj
2023-05-17 22:55 ` Jing Zhang
2023-05-18 21:08 ` Jitindar Singh, Suraj
2023-05-19 9:16 ` Marc Zyngier
2023-05-19 23:04 ` Jitindar Singh, Suraj
2023-05-20 8:45 ` Marc Zyngier [this message]
2023-05-19 23:25 ` Suraj Jitindar Singh
2023-05-16 10:37 ` [PATCH v8 0/6] Support writable CPU ID registers from userspace Shameerali Kolothum Thodi
2023-05-16 11:01 ` Marc Zyngier
2023-05-16 11:11 ` Shameerali Kolothum Thodi
2023-05-16 11:55 ` Cornelia Huck
2023-05-16 13:11 ` Marc Zyngier
2023-05-16 13:44 ` Shameerali Kolothum Thodi
2023-05-16 14:21 ` Cornelia Huck
2023-05-16 14:19 ` Cornelia Huck
2023-05-16 16:01 ` Marc Zyngier
2023-05-17 15:36 ` Cornelia Huck
2023-05-17 15:53 ` Marc Zyngier
2023-05-16 16:31 ` Oliver Upton
2023-05-16 16:44 ` Marc Zyngier
2023-05-16 16:57 ` Oliver Upton
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