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Fri, 17 Mar 2023 16:48:27 +0000 Date: Fri, 17 Mar 2023 16:48:26 +0000 Message-ID: <87zg8bgw85.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Joey Gouly , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH 2/2] KVM: arm64: Move FGT value configuration to vCPU state In-Reply-To: <855e60de-56c0-4500-a8ce-d79ffb0ed19d@sirena.org.uk> References: <20230301-kvm-arm64-fgt-v1-0-cfdf71ac67dc@kernel.org> <20230301-kvm-arm64-fgt-v1-2-cfdf71ac67dc@kernel.org> <867cvfyclz.wl-maz@kernel.org> <855e60de-56c0-4500-a8ce-d79ffb0ed19d@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 89.213.33.168 X-SA-Exim-Rcpt-To: broonie@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230317_094832_915425_95FB2080 X-CRM114-Status: GOOD ( 22.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 17 Mar 2023 13:49:44 +0000, Mark Brown wrote: > > On Fri, Mar 17, 2023 at 09:02:32AM +0000, Marc Zyngier wrote: > > Mark Brown wrote: > > > > + vcpu->arch.hfgrtr_el2 = 0; > > > + vcpu->arch.hfgwtr_el2 = 0; > > > Although this looks completely innocent, this actually have the effect > > of trapping the SMPRI_EL1 and TPIDR2_EL0 registers, something that is > > self documented in the current code, and that completely disappears > > with this patch. > > > This needs documenting by enumerating the sysregs that get trapped. > > That's an awful lot of registers with the fine grained traps, and when > extended to cover HFHxTR2 there's a bunch of RES0 bits intended for > future traps. It feels a bit unmanagable. I'd have expected something > more along the lines of "enable all traps other than...". The pattern > seemed to be more to have an explicit initialiser for the bits that are > set (eg, with CPACR_EL1) which was why I didn't put anything explicit. "an awful lot of registers" is exactly 3 registers as of ARMv8.8/9.3 that have a disable-trapping-when-set pattern. Maybe more in 9.4 and up, but if people can be bothered to write the tools/sysreg file, they can also document what gets implicitly trapped. This also outlines that ACCDATA_EL1 gets trapped while it wasn't explicitly trapped before, and that we don't have a handler for it. So we need an extensive documentation of what the 0 value covers, no ifs no buts. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel