From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E7C0C4338F for ; Thu, 12 Aug 2021 21:41:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2639060C3F for ; Thu, 12 Aug 2021 21:41:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2639060C3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u3xa6pDSsmGhyeImAJEeByMRkqVgiMPnozVThSMSWCE=; b=AQBR4mlAYS4a4r ijeRI2U5OF0Ri1dw0kjTURdxz0rtEQbGu1eQ4yIoCIaFEkLXRJW9PlFTaiCQViJ7X38JSy/K2kGjr sP4tXYXHDZKyixAtIU67LtWNEW4c+cN+7oo7qqzIVks3KI2wfE3RpHYL4RcHKAZC78WCyD/u/bZk+ /KhFLap/r12LpD12OWR5XNmAdhr1qFCMB1gz/4OyN8p6O9PwLt6Flej2uZQGyICVUwo+lIn8chdD4 B7z18FWfPmDwp6Uk7FRh38F41l8ckAw4OCWV8u05zJtUNN+EWuEbjLNioUgMNnWChRXiuyGgyRaSQ RGbR4fxiMiIQNrgOg6+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mEIPE-00BPaM-Ld; Thu, 12 Aug 2021 21:38:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mEIP8-00BPZo-Q9 for linux-arm-kernel@lists.infradead.org; Thu, 12 Aug 2021 21:38:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC6C11063; Thu, 12 Aug 2021 14:38:17 -0700 (PDT) Received: from e113632-lin (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C50D13F70D; Thu, 12 Aug 2021 14:38:16 -0700 (PDT) From: Valentin Schneider To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: Re: [PATCH v3 05/13] genirq: Let purely flow-masked ONESHOT irqs through unmask_threaded_irq() In-Reply-To: <87wnoq90wx.wl-maz@kernel.org> References: <20210629125010.458872-1-valentin.schneider@arm.com> <20210629125010.458872-6-valentin.schneider@arm.com> <87bl639l8n.wl-maz@kernel.org> <875ywa944c.mognet@arm.com> <87wnoq90wx.wl-maz@kernel.org> Date: Thu, 12 Aug 2021 22:38:11 +0100 Message-ID: <87zgtm7398.mognet@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210812_143822_982414_84076713 X-CRM114-Status: GOOD ( 17.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/08/21 15:45, Marc Zyngier wrote: > On Thu, 12 Aug 2021 14:36:35 +0100, > Valentin Schneider wrote: >> >> On 12/08/21 08:26, Marc Zyngier wrote: >> > On Tue, 29 Jun 2021 13:50:02 +0100, >> > Valentin Schneider wrote: >> >> diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c >> >> index ef30b4762947..e6d6d32ddcbc 100644 >> >> --- a/kernel/irq/manage.c >> >> +++ b/kernel/irq/manage.c >> >> @@ -1107,7 +1107,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, >> >> desc->threads_oneshot &= ~action->thread_mask; >> >> >> >> if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && >> >> - irqd_irq_masked(&desc->irq_data)) >> >> + (irqd_irq_masked(&desc->irq_data) | irqd_irq_flow_masked(&desc->irq_data))) >> >> unmask_threaded_irq(desc); >> > >> > The bitwise OR looks pretty odd. It is probably fine given that both >> > side of the expression are bool, but still. I can fix this locally. >> > >> >> Thomas suggested that back in v1: >> >> https://lore.kernel.org/lkml/87v98v4lan.ffs@nanos.tec.linutronix.de/ >> >> I did look at the (arm64) disassembly diff back then and was convinced by >> what I saw, though I'd have to go do that again as I can't remember much >> else. > > Ah, fair enough. > Either I didn't have my glasses on or had a different output back then, but I'm not so convinced anymore... (same result on both Ubuntu GCC 9.3.0 and 10.2 GCC release from Arm): Logical OR: 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 900: 37880040 tbnz w0, #17, 908 904: 36fffe60 tbz w0, #31, 8d0 908: aa1303e0 mov x0, x19 90c: 94000000 bl 0 Bitwise OR (aka the patch): 8f8: b9400020 ldr w0, [x1] 8fc: 3787fea0 tbnz w0, #16, 8d0 900: f26f001f tst x0, #0x20000 904: 7a400801 ccmp w0, #0x0, #0x1, eq // eq = none 908: 54fffe4a b.ge 8d0 // b.tcont 90c: aa1303e0 mov x0, x19 910: 94000000 bl 0 If I get this right... - TST sets the Z condition flag if bit 17 (masked) isn't set - CCMP sets the condition flags to - the same as SUBS(flags, 0) if bit 17 wasn't set - NZCV=0001 otherwise - B.GE branches if N==V Soooo - if we have bit 17 set, NZCV=0001, B.GE doesn't branch - if we don't have bit 17 but bit 31 (flow-masked), NZCV=1000 because this is signed 32-bit, so having bit 31 set makes the result of SUBS(flags, 0) negative, B.GE doesn't branch - if we have neither, NZCV=0XX0, B.GE branches So this does appear to do the right thing, at the cost of an extra instruction and a profound sense of dread to whoever stares at the disassembly. I guess it does save us a branch which could be mispredicted... > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel