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Mon, 23 Nov 2020 22:16:59 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 23 Nov 2020 22:16:59 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 23 Nov 2020 22:16:59 -0600 Received: from [10.24.69.198] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AO4Gs3L026518; Mon, 23 Nov 2020 22:16:54 -0600 Subject: Re: [PATCH v2 2/4] arm64: dts: ti: k3: squelch warnings regarding no #address-cells for interrupt-controller To: Nishanth Menon References: <20201117161942.38754-1-nsekhar@ti.com> <20201117161942.38754-3-nsekhar@ti.com> <20201118151259.kpag44djji4ssiup@eldest> <18e41dba-a3dd-308a-605e-63b76ca638e5@ti.com> <20201119132829.sr435jf6s4275q4i@boxlike> <313a9cd5-7411-4ae1-cde4-42a2c18d11e6@ti.com> <20201124012100.fq7w7bjxvewuhbt2@shirt> From: Sekhar Nori Message-ID: <8885dd79-061b-82e3-1aeb-a318f7d8256d@ti.com> Date: Tue, 24 Nov 2020 09:46:53 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20201124012100.fq7w7bjxvewuhbt2@shirt> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201123_231709_107493_A74DA733 X-CRM114-Status: GOOD ( 16.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Device Tree Mailing List , Grygorii Strashko , Lokesh Vutla , Andre Przywara , linux-kernel@vger.kernel.org, Faiz Abbas , Tero Kristo , Rob Herring , Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/11/20 6:51 AM, Nishanth Menon wrote: > On 09:45-20201123, Sekhar Nori wrote: >>>> The main reason I commented - is hope to get some clarification from DT maintainers. >>>> 90% of interrupt-controller nodes do not have #address-cells and I never seen in in GPIO nodes >>>> (most often is present in PCI and GIC nodes). >>>> and nobody seems fixing it. So, if we are going to move this direction it's reasonable to get clarification to be sure. >>>> >>>> And there is no "never" here - #address-cells always can be added if really required. >>> >>> >>> OK - as a GPIO node, but as an interrupt-controller node, I was >>> looking at [1] and wondering if that was the precedence. >>> >>> Yes, will be good to get direction from the DT maintainers on this >>> topic. >> >> Shall I respin this series with 2/4 dropped while we wait for decision >> on this? >> >> #address-cells warnings on interrupt controller can perhaps be handled >> all at once (there are many of those in existing DT anyway). >> >> GPIO is basic support and holds up many other modules (like MMC/SD). > > > There are'nt too many new patches in my queue that depends on GPIO, I'd > rather not introduce new warnings unless we are completely at a > stalemate. I'd rather use this opportunity to understand where what we > need to be doing. GPIO was originally submitted as part of 8 patch series titled "[PATCH 0/8] Add support for UHS modes in TI's J721e and J7200 boards" Rest of those patches need to be resubmitted after GPIO is accepted. Can you apply patch 1/4 at least. Its fairly non-controversial. It will help reduce patch backlog and fix some warnings too. Thanks, Sekhar _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel