From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD01CC3DA7F for ; Sun, 4 Aug 2024 13:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:Message-ID:References:In-Reply-To:Subject:Cc:To:From:Date: MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dj33eAXFyzvI5ou2nnBICX6LZsQd16Cx3Rd0uFjTv0I=; b=RA+6bPzw5a9YCoSJNpfYMKOTpk 7f/UI8eGEKbzdCXOWQr9uNNJkVPbBpv7GRH3fDq79P8L2w+EiCGAu6LlbUn0eW3gGKlATDr5n/Wcx UM3Ij9DC/SpybQbX/8oY6Sl5EVsgkzLV5EhKQCTHeTIwqA8P0g6LuHZUDZ9XhSmQr1CylAp/P6BMI bBZ1dNg+drQ1p/tP8RtX3cF46/ODYFL/AzSj/n5hWL5s/f1cp6tbBx6+4hItCPhxHWmCOk4P8qnJy lkBmgOezMR21JHK5lmeEPARiiWqwiNtY7X6FxsIR9KpzDlBiV7+HoKVpRpEOA6cAg29A0bwWlaXEN 9fX/jo6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sabFh-0000000DJrx-376I; Sun, 04 Aug 2024 13:26:25 +0000 Received: from mail.manjaro.org ([116.203.91.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sabFA-0000000DJnI-3JTP; Sun, 04 Aug 2024 13:25:55 +0000 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=manjaro.org; s=2021; t=1722777949; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dj33eAXFyzvI5ou2nnBICX6LZsQd16Cx3Rd0uFjTv0I=; b=KE2fnYngiIZRwc08+z2fGPsMrWbid9kHCO9DKLgyoIs+f6IfhVcaPNLCDktKOSF1mR3zIz zFPjUyE3fQ07sW4LiMaI4vDiWbdeEPBGO/INHePB+HwFOpJxPhkvwfp8tzwKFHBsZ23/0m QWEsM4lSj7QplRYd+xXDK7J885TPyVD7ScHCVOlLOcmmEZRKOnBfPQie6cRDOG2yMRDKXb b5xfV1GWYiMEan1GWeVBGXA8cGLnMdT6qDpI4PbAN00ZnGIdGqOmoFgrej917RTGoc1EFX Gx71jAzOPxXs+KcQxKBFeBU6jghBEq1RwX93Te8JsRsJjvWElTsSr7JA1ZHnow== Date: Sun, 04 Aug 2024 15:25:47 +0200 From: Dragan Simic To: Yao Zi Cc: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Greg Kroah-Hartman , Jiri Slaby , Chris Morgan , Jonas Karlman , Tim Lunn , Andy Yan , Muhammed Efe Cetin , Jagan Teki , Ondrej Jirman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC In-Reply-To: References: <20240803125510.4699-2-ziyao@disroot.org> <20240803125510.4699-5-ziyao@disroot.org> <56bd1478-ce8c-4c1d-ab16-afe4ad462bf5@kernel.org> Message-ID: <88dd5910904c03280f37ca0051f5de4e@manjaro.org> X-Sender: dsimic@manjaro.org Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Authentication-Results: ORIGINATING; auth=pass smtp.auth=dsimic@manjaro.org smtp.mailfrom=dsimic@manjaro.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240804_062553_471248_7D319F7D X-CRM114-Status: GOOD ( 22.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024-08-04 15:20, Yao Zi wrote: > On Sun, Aug 04, 2024 at 12:05:11PM +0200, Krzysztof Kozlowski wrote: >> On 03/08/2024 14:55, Yao Zi wrote: >> > This initial device tree describes CPU, interrupts and UART on the chip >> > and is able to boot into basic kernel with only UART. Cache information >> > is omitted for now as there is no precise documentation. Support for >> > other features will be added later. >> > >> > Signed-off-by: Yao Zi >> > --- >> > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++ >> > 1 file changed, 182 insertions(+) >> > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi >> > >> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi >> > new file mode 100644 >> > index 000000000000..77687d9e7e80 >> > --- /dev/null >> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi >> > @@ -0,0 +1,182 @@ >> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> > +/* >> > + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. >> > + * Copyright (c) 2024 Yao Zi >> > + */ >> > + >> > +#include >> > +#include >> > + >> > +/ { >> > + compatible = "rockchip,rk3528"; >> > + >> > + interrupt-parent = <&gic>; >> > + #address-cells = <2>; >> > + #size-cells = <2>; >> > + >> > + aliases { >> > + serial0 = &uart0; >> > + serial1 = &uart1; >> > + serial2 = &uart2; >> > + serial3 = &uart3; >> > + serial4 = &uart4; >> > + serial5 = &uart5; >> > + serial6 = &uart6; >> > + serial7 = &uart7; >> > + }; >> > + >> > + cpus { >> > + #address-cells = <1>; >> > + #size-cells = <0>; >> > + >> > + cpu-map { >> > + cluster0 { >> > + core0 { >> > + cpu = <&cpu0>; >> > + }; >> > + core1 { >> > + cpu = <&cpu1>; >> > + }; >> > + core2 { >> > + cpu = <&cpu2>; >> > + }; >> > + core3 { >> > + cpu = <&cpu3>; >> > + }; >> > + }; >> > + }; >> > + >> > + cpu0: cpu@0 { >> > + device_type = "cpu"; >> > + compatible = "arm,cortex-a53"; >> > + reg = <0x0>; >> > + enable-method = "psci"; >> > + }; >> > + >> > + cpu1: cpu@1 { >> > + device_type = "cpu"; >> > + compatible = "arm,cortex-a53"; >> > + reg = <0x1>; >> > + enable-method = "psci"; >> > + }; >> > + >> > + cpu2: cpu@2 { >> > + device_type = "cpu"; >> > + compatible = "arm,cortex-a53"; >> > + reg = <0x2>; >> > + enable-method = "psci"; >> > + }; >> > + >> > + cpu3: cpu@3 { >> > + device_type = "cpu"; >> > + compatible = "arm,cortex-a53"; >> > + reg = <0x3>; >> > + enable-method = "psci"; >> > + }; >> > + }; >> > + >> > + psci { >> > + compatible = "arm,psci-1.0", "arm,psci-0.2"; >> > + method = "smc"; >> > + }; >> > + >> > + timer { >> > + compatible = "arm,armv8-timer"; >> > + interrupts = , >> > + , >> > + , >> > + ; >> > + }; >> > + >> > + xin24m: xin24m { >> >> Please use name for all fixed clocks which matches current format >> recommendation: 'clock-([0-9]+|[a-z0-9-]+)+' > > Will be fixed in next revision. Hmm, why should we apply that rule to the xin24m clock, which is named exactly like that everywhere else in Rockchip SoC dtsi files? It's much better to remain consistent. >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1 >> >> > + compatible = "fixed-clock"; >> > + #clock-cells = <0>; >> > + clock-frequency = <24000000>; >> > + clock-output-names = "xin24m"; >> > + }; >> > + >> > + gic: interrupt-controller@fed01000 { >> >> Why this all is outside of SoC? > > Just as Heiko says, device tree for all other Rockchip SoCs don't have > a "soc" node. I didn't know why before but just follow the style. > > If you prefer add a soc node, I am willing to.